diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
| commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
| tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/long/30.eon/ref/arm | |
| parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
| download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz | |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/long/30.eon/ref/arm')
9 files changed, 520 insertions, 497 deletions
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index 5e5332f9b..b78535a02 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 @@ -493,7 +496,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index f3be2b346..56d7b7504 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 21 2011 14:34:16 -M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch -M5 started Feb 21 2011 14:41:06 +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:19:35 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -17,5 +17,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.210000 -Exiting @ tick 215422930500 because target called exit() +OO-style eon Time= 0.170000 +Exiting @ tick 173737299500 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index de918dfb0..a23b70561 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,130 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59988 # Simulator instruction rate (inst/s) -host_mem_usage 271504 # Number of bytes of host memory used -host_seconds 5747.46 # Real time elapsed on the host -host_tick_rate 37481445 # Simulator tick rate (ticks/s) +host_inst_rate 105768 # Simulator instruction rate (inst/s) +host_mem_usage 263952 # Number of bytes of host memory used +host_seconds 3300.30 # Real time elapsed on the host +host_tick_rate 52642890 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 344777343 # Number of instructions simulated -sim_seconds 0.215423 # Number of seconds simulated -sim_ticks 215422930500 # Number of ticks simulated +sim_insts 349065960 # Number of instructions simulated +sim_seconds 0.173737 # Number of seconds simulated +sim_ticks 173737299500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 29670488 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 36719835 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 7622671 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 36869177 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 36869177 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 28188953 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 5177396 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 20216884 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 26426271 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 53555 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3385203 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 19876693 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 36665151 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 7335349 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 30506630 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 6423122 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 417225904 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.826358 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.412065 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 340217087 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.026011 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.609311 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 233100746 55.87% 55.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 116424213 27.90% 83.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 32132757 7.70% 91.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 14133629 3.39% 94.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 7357055 1.76% 96.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 4244457 1.02% 97.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 2971889 0.71% 98.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1683762 0.40% 98.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 5177396 1.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 170345162 50.07% 50.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 99509001 29.25% 79.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 28782057 8.46% 87.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 16235874 4.77% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 9859908 2.90% 95.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 4137947 1.22% 96.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 2696620 0.79% 97.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2227396 0.65% 98.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 6423122 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 417225904 # Number of insts commited each cycle -system.cpu.commit.COM:count 344777955 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 340217087 # Number of insts commited each cycle +system.cpu.commit.COM:count 349066572 # Number of instructions committed system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 283262899 # Number of committed integer instructions. -system.cpu.commit.COM:loads 94652977 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 177028572 # Number of memory references committed +system.cpu.commit.COM:function_calls 6225112 # Number of function calls committed. +system.cpu.commit.COM:int_insts 287529355 # Number of committed integer instructions. +system.cpu.commit.COM:loads 94648992 # Number of loads committed +system.cpu.commit.COM:membars 11033 # Number of memory barriers committed +system.cpu.commit.COM:refs 177024829 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 9986408 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 344777955 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 3533298 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 48561453 # The number of squashed insts skipped by commit -system.cpu.committedInsts 344777343 # Number of Instructions Simulated -system.cpu.committedInsts_total 344777343 # Number of Instructions Simulated -system.cpu.cpi 1.249635 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.249635 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 98212603 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 32812.379110 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30419.186047 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 98209501 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 101784000 # number of ReadReq miss cycles +system.cpu.commit.branchMispredicts 3371287 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 349066572 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 3555471 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 38687255 # The number of squashed insts skipped by commit +system.cpu.committedInsts 349065960 # Number of Instructions Simulated +system.cpu.committedInsts_total 349065960 # Number of Instructions Simulated +system.cpu.cpi 0.995441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.995441 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 11396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 11394 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 97345834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33073.410778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30661.926872 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 97342735 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 102494500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 3102 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1382 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 52321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 3099 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1376 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 52830500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 29748.238774 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35491.403509 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 82044977 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 553168500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000227 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 18595 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 15745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 101150500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 1723 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 11142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 11142 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 82052672 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31425.125183 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35401.373723 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 82033500 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 602482500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 19172 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 16333 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 100504500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2850 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2839 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11781.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 39442.992998 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 19863.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 39324.588119 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 188500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 218500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 180276175 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30186.316081 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33582.385120 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180254478 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 654952500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000120 # miss rate for demand accesses -system.cpu.dcache.demand_misses 21697 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 17127 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 153471500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 179398506 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31654.483409 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33611.354669 # average overall mshr miss latency +system.cpu.dcache.demand_hits 179376235 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 704977000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses +system.cpu.dcache.demand_misses 22271 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 17709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 153335000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4570 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4562 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.755653 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3095.155896 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 180276175 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30186.316081 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33582.385120 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.753400 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3085.925842 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 179398506 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31654.483409 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33611.354669 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180254478 # number of overall hits -system.cpu.dcache.overall_miss_latency 654952500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000120 # miss rate for overall accesses -system.cpu.dcache.overall_misses 21697 # number of overall misses -system.cpu.dcache.overall_mshr_hits 17127 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 153471500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 179376235 # number of overall hits +system.cpu.dcache.overall_miss_latency 704977000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses +system.cpu.dcache.overall_misses 22271 # number of overall misses +system.cpu.dcache.overall_mshr_hits 17709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 153335000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4570 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4562 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1402 # number of replacements -system.cpu.dcache.sampled_refs 4570 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1404 # number of replacements +system.cpu.dcache.sampled_refs 4562 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3095.155896 # Cycle average of tags in use -system.cpu.dcache.total_refs 180254478 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3085.925842 # Cycle average of tags in use +system.cpu.dcache.total_refs 179398771 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1028 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 135683876 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 445047864 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 110691412 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 165193226 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 13510644 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 5657389 # Number of cycles decode is unblocking +system.cpu.dcache.writebacks 1024 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 177195286 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 71850 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 7266733 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 418101627 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 89070591 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 70339326 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 7142428 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 201892 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 3611883 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -146,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 36869177 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 45676128 # Number of cache lines fetched -system.cpu.fetch.Cycles 181360333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 631577 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 363476608 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 18583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9990877 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085574 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 45676128 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 29670488 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.843635 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 430736547 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.090672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.994313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 36665151 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 39333951 # Number of cache lines fetched +system.cpu.fetch.Cycles 76200894 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 219495 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 327214024 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 19976 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3525022 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.105519 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 39333951 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 27552233 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.941692 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 347359514 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.232140 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.649316 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 252892375 58.71% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 95422079 22.15% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21830959 5.07% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14061343 3.26% 89.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11029779 2.56% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8719423 2.02% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4691835 1.09% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4052981 0.94% 95.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18035773 4.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 271714378 78.22% 78.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9098002 2.62% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5614129 1.62% 82.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6550857 1.89% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5401109 1.55% 85.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4665359 1.34% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3626849 1.04% 88.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4186087 1.21% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36502744 10.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 430736547 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 185889152 # number of floating regfile reads -system.cpu.fp_regfile_writes 130863264 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 45676128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 11498.066424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 7998.605010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 45658544 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 202182000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000385 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 17584 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 738 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 134744500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000369 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 16846 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 347359514 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 185260821 # number of floating regfile reads +system.cpu.fp_regfile_writes 130652752 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 39333951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12067.997808 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8366.912236 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 39317524 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 198241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000418 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 16427 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 817 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 130607500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000397 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 15610 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2710.671100 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2518.739526 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 45676128 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 11498.066424 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 7998.605010 # average overall mshr miss latency -system.cpu.icache.demand_hits 45658544 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 202182000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000385 # miss rate for demand accesses -system.cpu.icache.demand_misses 17584 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 738 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 134744500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000369 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 16846 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 39333951 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12067.997808 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8366.912236 # average overall mshr miss latency +system.cpu.icache.demand_hits 39317524 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 198241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000418 # miss rate for demand accesses +system.cpu.icache.demand_misses 16427 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 817 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 130607500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000397 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 15610 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.897245 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1837.557197 # Average occupied blocks per context -system.cpu.icache.overall_accesses 45676128 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 11498.066424 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 7998.605010 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.894157 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1831.233820 # Average occupied blocks per context +system.cpu.icache.overall_accesses 39333951 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12067.997808 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8366.912236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 45658544 # number of overall hits -system.cpu.icache.overall_miss_latency 202182000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000385 # miss rate for overall accesses -system.cpu.icache.overall_misses 17584 # number of overall misses -system.cpu.icache.overall_mshr_hits 738 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 134744500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000369 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 16846 # number of overall MSHR misses +system.cpu.icache.overall_hits 39317524 # number of overall hits +system.cpu.icache.overall_miss_latency 198241000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000418 # miss rate for overall accesses +system.cpu.icache.overall_misses 16427 # number of overall misses +system.cpu.icache.overall_mshr_hits 817 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 130607500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000397 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 15610 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 14975 # number of replacements -system.cpu.icache.sampled_refs 16844 # Sample count of references to valid blocks. +system.cpu.icache.replacements 13743 # number of replacements +system.cpu.icache.sampled_refs 15610 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1837.557197 # Cycle average of tags in use -system.cpu.icache.total_refs 45658544 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1831.233820 # Cycle average of tags in use +system.cpu.icache.total_refs 39317524 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 109315 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 29572151 # Number of branches executed -system.cpu.iew.EXEC:nop 511948 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.857328 # Inst execution rate -system.cpu.iew.EXEC:refs 185716991 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 85614422 # Number of stores executed +system.cpu.idleCycles 115086 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 31830970 # Number of branches executed +system.cpu.iew.EXEC:nop 56108 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.053222 # Inst execution rate +system.cpu.iew.EXEC:refs 183288367 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 84683782 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 264871547 # num instructions consuming a value -system.cpu.iew.WB:count 365283823 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.549146 # average fanout of values written-back +system.cpu.iew.WB:consumers 326571947 # num instructions consuming a value +system.cpu.iew.WB:count 364037870 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.499993 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 145453119 # num instructions producing a value -system.cpu.iew.WB:rate 0.847829 # insts written-back per cycle -system.cpu.iew.WB:sent 366846883 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 10421797 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4450 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 108215518 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 3540937 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 11257763 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 93620838 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 393341940 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 100102569 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7587099 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 369376260 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 69 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 163283573 # num instructions producing a value +system.cpu.iew.WB:rate 1.047668 # insts written-back per cycle +system.cpu.iew.WB:sent 364350526 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3594029 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 769955 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 107131506 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 3647750 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 5567384 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 91507860 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 387756246 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 98604585 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2702902 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 365967822 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 137 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 13510644 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 176 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 7142428 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44317 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 37 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 651720 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 443 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 109 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1040195 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1660 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6487 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13562540 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 11245243 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6487 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2859143 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 7562654 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 856895426 # number of integer regfile reads -system.cpu.int_regfile_writes 187404557 # number of integer regfile writes -system.cpu.ipc 0.800234 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.800234 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 177809 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 44277 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 12482513 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 9132023 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 177809 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 383406 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3210623 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 849409468 # number of integer regfile reads +system.cpu.int_regfile_writes 186524631 # number of integer regfile writes +system.cpu.ipc 1.004580 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.004580 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 129916529 34.46% 34.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2146058 0.57% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 679 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 2 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 35.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6735975 1.79% 36.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8317099 2.21% 39.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3313873 0.88% 39.91% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1566398 0.42% 40.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20555034 5.45% 45.77% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7151488 1.90% 47.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7075439 1.88% 49.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.59% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 102612475 27.22% 76.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 87397021 23.18% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 127517311 34.59% 34.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 2147275 0.58% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 35.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684179 1.81% 36.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8181294 2.22% 39.20% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3298042 0.89% 40.10% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567223 0.43% 40.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20157898 5.47% 45.99% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7156749 1.94% 47.93% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077602 1.92% 49.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175287 0.05% 49.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 99210852 26.91% 76.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 85497009 23.19% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 376963359 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 6999234 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018567 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 368670724 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 6503476 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017640 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 202 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.07% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 70 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 715 0.01% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 145523 2.08% 2.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 588 0.01% 2.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 183278 2.62% 4.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4924135 70.35% 75.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1739680 24.86% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 17082 0.26% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.08% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1526 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 257921 3.97% 4.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 627 0.01% 4.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 182979 2.81% 7.15% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.15% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4701020 72.28% 79.44% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1337212 20.56% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 430736547 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.875160 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.210569 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 347359514 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.061352 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.398972 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 218916849 50.82% 50.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 123149552 28.59% 79.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 45929825 10.66% 90.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 20859984 4.84% 94.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 13764585 3.20% 98.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 5289881 1.23% 99.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2150519 0.50% 99.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 439470 0.10% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 235882 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 164898974 47.47% 47.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 92888126 26.74% 74.21% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 38718431 11.15% 85.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 21127173 6.08% 91.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 18826760 5.42% 96.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 6953193 2.00% 98.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 2902778 0.84% 99.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 878088 0.25% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 165991 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 430736547 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.874938 # Inst issue rate -system.cpu.iq.fp_alu_accesses 122762431 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 242026966 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 116081453 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 130324765 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 261200162 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 950433097 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 249202370 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 307537991 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 389289055 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 376963359 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3540937 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 45027872 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 797564 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7639 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 100142647 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 347359514 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.061000 # Inst issue rate +system.cpu.iq.fp_alu_accesses 120434049 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 238151015 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 116197950 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 135223001 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 254740151 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 853728758 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 247839920 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 290561942 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 384041147 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 368670724 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3658991 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 38001894 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 675335 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 103520 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 93798234 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -404,106 +416,107 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 2850 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.695376 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31218.319802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_accesses 2839 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34387.668320 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.927711 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 97485500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.994035 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 2833 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88441500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994035 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 2833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 18566 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34300.665596 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.036271 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 14209 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 149448000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.234676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4357 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 133950500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231660 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4301 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1028 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1028 # number of Writeback hits +system.cpu.l2cache.ReadExReq_miss_latency 97042000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.994012 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 2822 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88136500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994012 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 2822 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 17333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34339.384829 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.919476 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 13009 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 148483500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.249466 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4324 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 133081000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4272 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1024 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1024 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.731600 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.521086 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 21416 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34344.019471 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.535184 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 14226 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246933500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.335730 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7190 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 222392000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.333115 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 20172 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34358.452281 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31183.746828 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 13026 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 245525500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.354253 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7146 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 221217500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.351676 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7094 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.104167 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3413.355578 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 381.656201 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 21416 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34344.019471 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.535184 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.103741 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011357 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3399.382463 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 372.162474 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 20172 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34358.452281 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31183.746828 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 14226 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246933500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.335730 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7190 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 222392000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.333115 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7134 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 13026 # number of overall hits +system.cpu.l2cache.overall_miss_latency 245525500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.354253 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7146 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 52 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 221217500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.351676 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7094 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 55 # number of replacements -system.cpu.l2cache.sampled_refs 5231 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 53 # number of replacements +system.cpu.l2cache.sampled_refs 5193 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3795.011778 # Cycle average of tags in use -system.cpu.l2cache.total_refs 14289 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3771.544937 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13092 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 34606296 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 43565672 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 108215518 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93620838 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1021297842 # number of misc regfile reads -system.cpu.misc_regfile_writes 43097547 # number of misc regfile writes -system.cpu.numCycles 430845862 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 57304786 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 64927444 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 107131506 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91507860 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 972227372 # number of misc regfile reads +system.cpu.misc_regfile_writes 43097542 # number of misc regfile writes +system.cpu.numCycles 347474600 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2009946 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 340171955 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2410 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 122720761 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 4353275 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 1678808180 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 427512132 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 413848551 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 159404950 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 13510644 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15892137 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 73676593 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 836456573 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 842351607 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 117198109 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 12788197 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 37692284 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3543781 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 805385393 # The number of ROB reads -system.cpu.rob.rob_writes 800205802 # The number of ROB writes -system.cpu.timesIdled 2213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 9320114 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 344460442 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1304973 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 97580493 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 14494347 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1601896967 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 403426158 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 392194299 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 65706997 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 7142428 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 28947021 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47733854 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 827888222 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 774008745 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 138662461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 12572275 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 80571383 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 3693310 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 721545269 # The number of ROB reads +system.cpu.rob.rob_writes 782665651 # The number of ROB writes +system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 191 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini index a5b41f00b..392543608 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -66,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout index 934921226..ec0472b91 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:25 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:29:05 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.210000 -Exiting @ tick 210200321500 because target called exit() +Exiting @ tick 212344048000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt index f26b1f1eb..d8a1a1d08 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 829275 # Simulator instruction rate (inst/s) -host_mem_usage 237784 # Number of bytes of host memory used -host_seconds 415.76 # Real time elapsed on the host -host_tick_rate 505582613 # Simulator tick rate (ticks/s) +host_inst_rate 1495798 # Simulator instruction rate (inst/s) +host_mem_usage 254688 # Number of bytes of host memory used +host_seconds 233.36 # Real time elapsed on the host +host_tick_rate 909925289 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 344777955 # Number of instructions simulated -sim_seconds 0.210200 # Number of seconds simulated -sim_ticks 210200321500 # Number of ticks simulated +sim_insts 349065408 # Number of instructions simulated +sim_seconds 0.212344 # Number of seconds simulated +sim_ticks 212344048000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 420400644 # number of cpu cycles simulated +system.cpu.numCycles 424688097 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 420400644 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 424688097 # Number of busy cycles +system.cpu.num_conditional_control_insts 16255902 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 12435295 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 344777955 # Number of instructions executed -system.cpu.num_int_alu_accesses 283262903 # Number of integer alu accesses -system.cpu.num_int_insts 283262903 # number of integer instructions -system.cpu.num_int_register_reads 1207980255 # number of times the integer registers were read -system.cpu.num_int_register_writes 211974282 # number of times the integer registers were written -system.cpu.num_load_insts 94652977 # Number of load instructions -system.cpu.num_mem_refs 177028576 # number of memory refs +system.cpu.num_insts 349065408 # Number of instructions executed +system.cpu.num_int_alu_accesses 287528428 # Number of integer alu accesses +system.cpu.num_int_insts 287528428 # number of integer instructions +system.cpu.num_int_register_reads 1216522338 # number of times the integer registers were read +system.cpu.num_int_register_writes 216261597 # number of times the integer registers were written +system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.workload.PROG:num_syscalls 191 # Number of system calls diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini index 9c15d1771..8ca4edc2e 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 @@ -166,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout index 1f52687a3..3a8c991e1 100755 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:00:13 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:10:13 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.520000 -Exiting @ tick 525825884000 because target called exit() +Exiting @ tick 525854475000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt index b6636f892..5afa5e2b9 100644 --- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,27 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 394687 # Simulator instruction rate (inst/s) -host_mem_usage 245492 # Number of bytes of host memory used -host_seconds 872.59 # Real time elapsed on the host -host_tick_rate 602604420 # Simulator tick rate (ticks/s) +host_inst_rate 633525 # Simulator instruction rate (inst/s) +host_mem_usage 262364 # Number of bytes of host memory used +host_seconds 550.39 # Real time elapsed on the host +host_tick_rate 955417914 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 344399678 # Number of instructions simulated -sim_seconds 0.525826 # Number of seconds simulated -sim_ticks 525825884000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94585118 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 79912000 # number of ReadReq miss cycles +sim_insts 348687131 # Number of instructions simulated +sim_seconds 0.525854 # Number of seconds simulated +sim_ticks 525854475000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 10895 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 94571611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94570005 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 79898000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1607 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1606 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 75080000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1606 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 10895 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 82060700 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses @@ -30,47 +34,47 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # m system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 53599.464166 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 50599.464166 # average overall mshr miss latency -system.cpu.dcache.demand_hits 176645818 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 240072000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 176624288 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 53608.307280 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency +system.cpu.dcache.demand_hits 176619810 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 240058000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4479 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 4478 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 226635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 226624000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4479 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4478 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3079.431639 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 53599.464166 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 50599.464166 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.751562 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3078.396238 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 176624288 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 176645818 # number of overall hits -system.cpu.dcache.overall_miss_latency 240072000 # number of overall miss cycles +system.cpu.dcache.overall_hits 176619810 # number of overall hits +system.cpu.dcache.overall_miss_latency 240058000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4479 # number of overall misses +system.cpu.dcache.overall_misses 4478 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 226635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 226624000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4479 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3079.431639 # Cycle average of tags in use -system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use +system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 998 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses @@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 348627536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 348660359 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 348611933 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 348644756 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses @@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # ms system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 22342.622124 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 348627536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 348660359 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency -system.cpu.icache.demand_hits 348611933 # number of demand (read+write) hits +system.cpu.icache.demand_hits 348644756 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses @@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses 15603 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1766.001397 # Average occupied blocks per context -system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.862297 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1765.984158 # Average occupied blocks per context +system.cpu.icache.overall_accesses 348660359 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 348611933 # number of overall hits +system.cpu.icache.overall_hits 348644756 # number of overall hits system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses system.cpu.icache.overall_misses 15603 # number of overall misses @@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 13796 # number of replacements system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1766.001397 # Cycle average of tags in use -system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use +system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses 2856 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 17209 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 13233 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 13232 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.231087 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 0.231100 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.725579 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 20081 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 13249 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 13248 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.340255 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.340272 # miss rate for demand accesses system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.340255 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.340272 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.010426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3134.106018 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 341.623002 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.095644 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 13249 # number of overall hits +system.cpu.l2cache.overall_hits 13248 # number of overall hits system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.340255 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses system.cpu.l2cache.overall_misses 6833 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.340255 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 48 # number of replacements system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3475.729020 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13309 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1051651768 # number of cpu cycles simulated +system.cpu.numCycles 1051708950 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1051651768 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 1051708950 # Number of busy cycles +system.cpu.num_conditional_control_insts 16255901 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 12435295 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 344399678 # Number of instructions executed -system.cpu.num_int_alu_accesses 283262902 # Number of integer alu accesses -system.cpu.num_int_insts 283262902 # number of integer instructions -system.cpu.num_int_register_reads 1344047799 # number of times the integer registers were read -system.cpu.num_int_register_writes 212263713 # number of times the integer registers were written -system.cpu.num_load_insts 94652977 # Number of load instructions -system.cpu.num_mem_refs 177028576 # number of memory refs +system.cpu.num_insts 348687131 # Number of instructions executed +system.cpu.num_int_alu_accesses 287528427 # Number of integer alu accesses +system.cpu.num_int_insts 287528427 # number of integer instructions +system.cpu.num_int_register_reads 1352596558 # number of times the integer registers were read +system.cpu.num_int_register_writes 216551028 # number of times the integer registers were written +system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024357 # number of memory refs system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.workload.PROG:num_syscalls 191 # Number of system calls |