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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-08-17 05:06:22 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-08-17 05:06:22 -0700
commit0f8b5afd7ad82fda05c3ad42cda4f9046992428d (patch)
tree794e8480ec916aa1b7da4c756f71ae1f6b1ffec7 /tests/long/30.eon/ref/arm
parent0685ae7a2dbceaa2b9b264a57c9d5f82868e777e (diff)
downloadgem5-0f8b5afd7ad82fda05c3ad42cda4f9046992428d.tar.xz
tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
Diffstat (limited to 'tests/long/30.eon/ref/arm')
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini2
-rw-r--r--tests/long/30.eon/ref/arm/linux/simple-timing/config.ini4
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index 0f7678eb4..0795e438f 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -74,7 +74,7 @@ block_size=64
bus_id=0
clock=1000
header_cycles=1
-responder_set=false
+use_default_range=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index 3e8fe5eab..09f490b9e 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -142,7 +142,7 @@ block_size=64
bus_id=0
clock=1000
header_cycles=1
-responder_set=false
+use_default_range=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -174,7 +174,7 @@ block_size=64
bus_id=0
clock=1000
header_cycles=1
-responder_set=false
+use_default_range=false
width=64
port=system.physmem.port[0] system.cpu.l2cache.mem_side