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author | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
commit | a7e27f9a82300f213b268264e1dede222d26bd4d (patch) | |
tree | 905f84d6e06111d4a243c18a1899e932646bdced /tests/long/30.eon/ref | |
parent | 2342aa2ebbb9dfe232eafcd20f01a8dd95ebfcc0 (diff) | |
download | gem5-a7e27f9a82300f213b268264e1dede222d26bd4d.tar.xz |
tests: updates for stat name change
Diffstat (limited to 'tests/long/30.eon/ref')
4 files changed, 32 insertions, 32 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index caf1c0c92..1209b95f2 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:24 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:51 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 4140bf39e..d0a61b61f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 334419 # Simulator instruction rate (inst/s) -host_mem_usage 210864 # Number of bytes of host memory used -host_seconds 1123.07 # Real time elapsed on the host -host_tick_rate 100628798 # Simulator tick rate (ticks/s) +host_inst_rate 199356 # Simulator instruction rate (inst/s) +host_mem_usage 214136 # Number of bytes of host memory used +host_seconds 1883.94 # Real time elapsed on the host +host_tick_rate 59987309 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574812 # Number of instructions simulated sim_seconds 0.113013 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 51 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 9813191 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 192371 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10208559 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5629 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 192417 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 12228157 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 12856211 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10208559 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 5629 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 192417 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 12228157 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 12856211 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 09bb8bdda..41f4f6ce7 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:56:09 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:25:17 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 22fc80d01..76b5527a0 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 250845 # Simulator instruction rate (inst/s) -host_mem_usage 223896 # Number of bytes of host memory used -host_seconds 1391.56 # Real time elapsed on the host -host_tick_rate 109041329 # Simulator tick rate (ticks/s) +host_inst_rate 153284 # Simulator instruction rate (inst/s) +host_mem_usage 226404 # Number of bytes of host memory used +host_seconds 2277.25 # Real time elapsed on the host +host_tick_rate 66631737 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 349065985 # Number of instructions simulated sim_seconds 0.151737 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 5956648 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 247 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 3624729 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 41298 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 165832 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9469235 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 6767279 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3624729 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 41298 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 165832 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 270 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 9469235 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 6767279 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 165832 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 360118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3215056 # Number of branches that were predicted taken incorrectly |