alpha:o3:simple: update simout/err files

A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning

Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.

1 files changed, 39 insertions, 39 deletions

diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index f1d866c8d..b6ea3474a 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5736498                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202144                       # Number of bytes of host memory used
-host_seconds                                   350.21                       # Real time elapsed on the host
-host_tick_rate                             2868866718                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  1.004711                       # Number of seconds simulated
 sim_ticks                                1004710587000                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                722298387                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    721864922                       # DTB hits
-system.cpu.dtb.data_misses                     433465                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3394241                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1697486503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 190248                       # Number of bytes of host memory used
+host_seconds                                   591.88                       # Real time elapsed on the host
+sim_insts                                  2008987605                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                    511070026                       # DTB read hits
 system.cpu.dtb.read_misses                     418884                       # DTB read misses
-system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
 system.cpu.dtb.write_hits                   210794896                       # DTB write hits
 system.cpu.dtb.write_misses                     14581                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses              2009421175                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
+system.cpu.dtb.data_hits                    721864922                       # DTB hits
+system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                722298387                       # DTB accesses
 system.cpu.itb.fetch_hits                  2009421070                       # ITB hits
 system.cpu.itb.fetch_misses                       105                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses              2009421175                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
 system.cpu.numCycles                       2009421175                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                 2009421175                       # Number of busy cycles
-system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
-system.cpu.num_fp_insts                      71831671                       # number of float instructions
-system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
-system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
 system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
+system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1779374816                       # number of integer instructions
+system.cpu.num_fp_insts                      71831671                       # number of float instructions
 system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
 system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
-system.cpu.num_load_insts                   511488910                       # Number of load instructions
+system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
 system.cpu.num_mem_refs                     722298387                       # number of memory refs
+system.cpu.num_load_insts                   511488910                       # Number of load instructions
 system.cpu.num_store_insts                  210809477                       # Number of store instructions
-system.cpu.workload.num_syscalls                   39                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 2009421175                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------