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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt | |
parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt')
-rw-r--r-- | tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt | 60 |
1 files changed, 38 insertions, 22 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index ea21ed74e..4725fc27c 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1536320 # Simulator instruction rate (inst/s) -host_mem_usage 206288 # Number of bytes of host memory used -host_seconds 1307.66 # Real time elapsed on the host -host_tick_rate 2116487900 # Simulator tick rate (ticks/s) +host_inst_rate 1524477 # Simulator instruction rate (inst/s) +host_mem_usage 188336 # Number of bytes of host memory used +host_seconds 1317.82 # Real time elapsed on the host +host_tick_rate 2100501698 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987607 # Number of instructions simulated -sim_seconds 2.767652 # Number of seconds simulated -sim_ticks 2767652365000 # Number of ticks simulated +sim_insts 2008987605 # Number of instructions simulated +sim_seconds 2.768086 # Number of seconds simulated +sim_ticks 2768085828000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.361611 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.361643 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 795826000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 795905000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks -system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 722298387 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 721864922 # DTB hits +system.cpu.dtb.misses 433465 # DTB misses +system.cpu.dtb.read_accesses 511488910 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 511070026 # DTB read hits +system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.write_accesses 210809477 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 210794896 # DTB write hits +system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 15691.959230 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 166272000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # ms system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 15691.959230 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency -system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 166272000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 10596 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15691.959230 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2008977012 # number of overall hits +system.cpu.icache.overall_hits 2009410475 # number of overall hits system.cpu.icache.overall_miss_latency 166272000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.559322 # Cycle average of tags in use -system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1478.559335 # Cycle average of tags in use +system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2009421176 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2009421071 # ITB hits +system.cpu.itb.misses 105 # ITB misses system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1412930 # number of replacements system.cpu.l2cache.sampled_refs 1445479 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31165.183060 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31165.186472 # Cycle average of tags in use system.cpu.l2cache.total_refs 22612 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2767652365000 # number of cpu cycles simulated -system.cpu.num_insts 2008987607 # Number of instructions executed -system.cpu.num_refs 722390435 # Number of memory references +system.cpu.numCycles 2768085828000 # number of cpu cycles simulated +system.cpu.num_insts 2008987605 # Number of instructions executed +system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- |