Regression: Update stats for cache changes.

--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1

2 files changed, 126 insertions, 111 deletions

diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index dd36bbf60..31abd8f36 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
@@ -24,27 +24,28 @@ max_loads_any_thread=0
 phase=0
 progress_interval=0
 system=system
+tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
 prefetch_miss=false
 prefetch_past_page=false
 prefetch_policy=none
@@ -52,12 +53,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=262144
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
 prefetch_miss=false
 prefetch_past_page=false
 prefetch_policy=none
@@ -90,12 +89,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=131072
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
 prefetch_miss=false
 prefetch_past_page=false
 prefetch_policy=none
@@ -128,12 +125,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=2097152
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -151,6 +146,9 @@ responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
+[system.cpu.tracer]
+type=ExeTracer
+
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
@@ -174,7 +172,7 @@ bus_id=0
 clock=1000
 responder_set=false
 width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
index 6aa1ee5aa..ea21ed74e 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 622738                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 156744                       # Number of bytes of host memory used
-host_seconds                                  3226.05                       # Real time elapsed on the host
-host_tick_rate                              852686846                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1536320                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206288                       # Number of bytes of host memory used
+host_seconds                                  1307.66                       # Real time elapsed on the host
+host_tick_rate                             2116487900                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987607                       # Number of instructions simulated
-sim_seconds                                  2.750814                       # Number of seconds simulated
-sim_ticks                                2750814393000                       # Number of ticks simulated
+sim_seconds                                  2.767652                       # Number of seconds simulated
+sim_ticks                                2767652365000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    20372446000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    36307464000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  18914254000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  33391080000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     998252000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    926300000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             210720109                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    1869675000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000355                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               74787                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   1720101000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000355                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          74787                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13966.461980                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     21370698000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 24903.889094                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22903.889094                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               720331943                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     38177139000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002124                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1532979                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  19840554000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  35111181000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002124                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1532979                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13966.461980                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24903.889094                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22903.889094                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              720334778                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    21370698000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1530144                       # number of overall misses
+system.cpu.dcache.overall_hits              720331943                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    38177139000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002124                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1532979                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  19840554000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  35111181000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002124                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1532979                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                1526048                       # number of replacements
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.422371                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.361611                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              702832000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              795826000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                    74589                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         2008987608                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12448.659872                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 15691.959230                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             2008977012                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      131906000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      166272000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    121310000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    145080000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          2008987608                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12448.659872                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 15691.959230                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              2008977012                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       131906000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       166272000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    121310000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    145080000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses         2008987608                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12448.659872                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 15691.959230                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             2008977012                       # number of overall hits
-system.cpu.icache.overall_miss_latency      131906000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      166272000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                10596                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    121310000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    145080000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,61 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                   9046                       # number of replacements
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1478.610505                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1478.559322                       # Cycle average of tags in use
 system.cpu.icache.total_refs               2008977012                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses           1540740                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        13000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency   1582944000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             71952                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    791472000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        71952                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           1468788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 33878                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   19589206000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.978012                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1506862                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  16575482000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.978012                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1506862                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits                 20497                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   31862402000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.986045                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1448291                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  15931201000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.986045                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1448291                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses           2835                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 21821.516755                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency     61864000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses             2835                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency     31185000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses         2835                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses           74589                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               73515                       # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate       0.014399                       # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses              1074                       # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate     0.014399                       # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses         1074                       # number of Writeback MSHR misses
+system.cpu.l2cache.Writeback_miss_rate              1                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses             74589                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate            1                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses        74589                       # number of Writeback MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.071269                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.015643                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  33878                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    19589206000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.978012                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1506862                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  20497                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    33445346000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.986697                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1520243                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  16575482000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.978012                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1506862                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  16722673000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.986697                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1520243                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses           1615329                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12990.740986                       # average overall miss latency
+system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                107393                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   19589206000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.933516                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1507936                       # number of overall misses
+system.cpu.l2cache.overall_hits                 20497                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   33445346000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.986697                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1520243                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  16575482000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.932851                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1506862                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  16722673000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.986697                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1520243                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -204,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued            0
 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements               1474094                       # number of replacements
-system.cpu.l2cache.sampled_refs               1506862                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1412930                       # number of replacements
+system.cpu.l2cache.sampled_refs               1445479                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32753.638584                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  107393                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle            2394479000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66804                       # number of writebacks
+system.cpu.l2cache.tagsinuse             31165.183060                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   22612                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     2750814393000                       # number of cpu cycles simulated
+system.cpu.numCycles                     2767652365000                       # number of cpu cycles simulated
 system.cpu.num_insts                       2008987607                       # Number of instructions executed
 system.cpu.num_refs                         722390435                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls