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authorLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
commitee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch)
tree93b9bd8be890468c550b85eae4b467285b4d6811 /tests/long/40.perlbmk/ref/alpha
parent7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff)
downloadgem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/long/40.perlbmk/ref/alpha')
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt16
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini2
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr2
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt8
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini10
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr2
-rwxr-xr-xtests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt16
12 files changed, 54 insertions, 38 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 451db988f..a58d921a8 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index 01b34fd92..f8c1ec2f3 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
@@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index ab163e0dc..6590e3c76 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:52:13
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:45:31
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 6f8327e62..6efaa543d 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 233856 # Simulator instruction rate (inst/s)
-host_mem_usage 197400 # Number of bytes of host memory used
-host_seconds 7795.57 # Real time elapsed on the host
-host_tick_rate 90456464 # Simulator tick rate (ticks/s)
+host_inst_rate 178423 # Simulator instruction rate (inst/s)
+host_mem_usage 199584 # Number of bytes of host memory used
+host_seconds 10217.56 # Real time elapsed on the host
+host_tick_rate 69014447 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.705159 # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 1534074 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.104513 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses 9768 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.788136 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1614.102824 # Average occupied blocks per context
system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses 1511777 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.927694 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.046416 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 30398.691034 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1520.954518 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index d69895fd2..09e561461 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index 01b34fd92..f8c1ec2f3 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 867a8e254..2679d4b08 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:41:45
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:10:59
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 587f67841..93699388f 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3366150 # Simulator instruction rate (inst/s)
-host_mem_usage 202468 # Number of bytes of host memory used
-host_seconds 596.82 # Real time elapsed on the host
-host_tick_rate 1683437750 # Simulator tick rate (ticks/s)
+host_inst_rate 2073139 # Simulator instruction rate (inst/s)
+host_mem_usage 190360 # Number of bytes of host memory used
+host_seconds 969.06 # Real time elapsed on the host
+host_tick_rate 1036792835 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 066cbfff7..8af60fc8a 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index 01b34fd92..f8c1ec2f3 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 81c2e87d9..effc9024e 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:09:09
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 01:51:28
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 93430ba50..f1307660f 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2471520 # Simulator instruction rate (inst/s)
-host_mem_usage 211800 # Number of bytes of host memory used
-host_seconds 812.86 # Real time elapsed on the host
-host_tick_rate 3463041314 # Simulator tick rate (ticks/s)
+host_inst_rate 1237577 # Simulator instruction rate (inst/s)
+host_mem_usage 198020 # Number of bytes of host memory used
+host_seconds 1623.32 # Real time elapsed on the host
+host_tick_rate 1734066560 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1532979 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999804 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.198740 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 10596 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.721885 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1478.420115 # Average occupied blocks per context
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 1511420 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.926943 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.046880 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 30374.076068 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1536.161417 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency