diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
| commit | 5d5b0f49cc125973fb7048ad86bf85ab5ed57772 (patch) | |
| tree | 0840a5055d8d8103eb22bcbe1ad90498e3db8aee /tests/long/40.perlbmk/ref/arm/linux | |
| parent | d0b0a555151232566550c837f9d4d061bf3d4686 (diff) | |
| download | gem5-5d5b0f49cc125973fb7048ad86bf85ab5ed57772.tar.xz | |
Stats: Update stats for minor O3 changes below.
Diffstat (limited to 'tests/long/40.perlbmk/ref/arm/linux')
| -rwxr-xr-x | tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1000 |
2 files changed, 504 insertions, 504 deletions
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 40b1b56a0..bf375000b 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 4 2011 13:56:47 -M5 started May 4 2011 14:08:54 -M5 executing on nadc-0364 +M5 compiled May 16 2011 15:11:25 +M5 started May 16 2011 15:11:57 +M5 executing on nadc-0271 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1391,4 +1391,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 796501458500 because target called exit() +Exiting @ tick 795626752000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 1bd5ced79..ce16cf8d2 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,530 +1,530 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 152621 # Simulator instruction rate (inst/s) -host_mem_usage 267940 # Number of bytes of host memory used -host_seconds 12353.14 # Real time elapsed on the host -host_tick_rate 64477641 # Simulator tick rate (ticks/s) +sim_seconds 0.795627 # Number of seconds simulated +sim_ticks 795626752000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1885343121 # Number of instructions simulated -sim_seconds 0.796501 # Number of seconds simulated -sim_ticks 796501458500 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 295401459 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 412226769 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 2841374 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 40219938 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 399767362 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 521351365 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 53524846 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 45744525 # The number of times a branch was mispredicted -system.cpu.commit.branches 291352099 # Number of branches committed -system.cpu.commit.bw_lim_events 67684151 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1885354137 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 211786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1014250107 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1409452320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.337650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.030019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 650998601 46.19% 46.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 389487426 27.63% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 134882374 9.57% 83.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70608044 5.01% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45598376 3.24% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18595515 1.32% 92.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23751287 1.69% 94.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 7846546 0.56% 95.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67684151 4.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1409452320 # Number of insts commited each cycle -system.cpu.commit.count 1885354137 # Number of instructions committed -system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.int_insts 1653713091 # Number of committed integer instructions. -system.cpu.commit.loads 631390736 # Number of loads committed -system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.refs 908389587 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1885343121 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885343121 # Number of Instructions Simulated -system.cpu.cpi 0.844941 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.844941 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 16769 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 16766 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.000179 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 708570219 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34295.515999 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34092.262926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 706637503 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 66283492500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002728 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1932716 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 469902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 49870639500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1462814 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 13539 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 13539 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35038.454246 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32465.652371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276128758 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28273229500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 806920 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 734193 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2361129500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72727 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15250 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 640.035711 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 985505897 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34514.337671 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34015.222648 # average overall mshr miss latency -system.cpu.dcache.demand_hits 982766261 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94556722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2739636 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1204095 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 52231769000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001558 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1535541 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.850284 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 985505897 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34514.337671 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34015.222648 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 982766261 # number of overall hits -system.cpu.dcache.overall_miss_latency 94556722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2739636 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1204095 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 52231769000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001558 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1535541 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1531438 # number of replacements -system.cpu.dcache.sampled_refs 1535534 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.850284 # Cycle average of tags in use -system.cpu.dcache.total_refs 982796595 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 325357000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107000 # number of writebacks -system.cpu.decode.BlockedCycles 41214762 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 11076 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 76817010 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 3347910149 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 727407671 # Number of cycles decode is idle -system.cpu.decode.RunCycles 639439291 # Number of cycles decode is running -system.cpu.decode.SquashCycles 146381913 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 20384 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 1390594 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses +host_inst_rate 37469 # Simulator instruction rate (inst/s) +host_tick_rate 15812352 # Simulator tick rate (ticks/s) +host_mem_usage 261444 # Number of bytes of host memory used +host_seconds 50316.79 # Real time elapsed on the host +sim_insts 1885343131 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 521351365 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 363393229 # Number of cache lines fetched -system.cpu.fetch.Cycles 657902932 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 20866192 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2539704301 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 47134046 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.327276 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 363393229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 348926305 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.594287 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1555834231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.199016 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.044014 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1411 # Number of system calls +system.cpu.numCycles 1591253505 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 519677239 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 398144928 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 40174420 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 410482703 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 293585496 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 53540823 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2841317 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 361951635 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2537428028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 519677239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 347126319 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 659124412 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 47088491 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 166 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 361951635 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 20842559 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1554259692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.199934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.044955 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 897966873 57.72% 57.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 37681413 2.42% 60.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 106074065 6.82% 66.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 61536348 3.96% 70.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 89725743 5.77% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53094530 3.41% 80.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35033115 2.25% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 45486191 2.92% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 229235953 14.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 895170810 57.59% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 41935957 2.70% 60.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 103275417 6.64% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 61539532 3.96% 70.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 89553793 5.76% 76.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 52982183 3.41% 80.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34961510 2.25% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 45455804 2.92% 85.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 229384686 14.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1555834231 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 69468816 # number of floating regfile reads -system.cpu.fp_regfile_writes 51556158 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 363393229 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9064.622402 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5743.022314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 363365607 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 250383000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1554259692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.326584 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.594610 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 723197107 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 41283634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 642007597 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1402750 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 146368604 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 76799900 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11033 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3347346347 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 20349 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 146368604 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 756568519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 25444222 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3271742 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 608636712 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13969893 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3194137589 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3931047 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7404635 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 3358259430 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 15045243779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14391074287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 654169492 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993168551 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1365090874 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 254462 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 254764 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 34849726 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 925173948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 465395627 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 97302082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144361448 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889677990 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 244825 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2448298992 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 12457526 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 987757973 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2669097969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 33037 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1554259692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.575219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.653577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 571543598 36.77% 36.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 302403348 19.46% 56.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 272921305 17.56% 73.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 170079995 10.94% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 141872535 9.13% 93.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 62133878 4.00% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24302902 1.56% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6180941 0.40% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2821190 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1554259692 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5100 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23970 0.03% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 52395536 69.00% 69.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23506568 30.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1194651657 48.80% 48.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11220052 0.46% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 8628 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 49.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 49.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 6176938 0.25% 49.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 25435651 1.04% 50.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 792339955 32.36% 83.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 410214348 16.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2448298992 # Type of FU issued +system.cpu.iq.rate 1.538598 # Inst issue rate +system.cpu.iq.fu_busy_cnt 75931174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.031014 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6412694569 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3775928903 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2259827011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 126551807 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 103128995 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 57766877 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2458203699 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66026467 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 38019387 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 293783209 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1377644 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2672008 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 188396774 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 146368604 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17402025 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3966817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2889988302 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 9053008 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 925173948 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 465395627 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 232022 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2656731 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 304 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2672008 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 37424548 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 12425696 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 49850244 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2354181989 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 757207603 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94117003 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 65487 # number of nop insts executed +system.cpu.iew.exec_refs 1128829223 # number of memory reference insts executed +system.cpu.iew.exec_branches 348669519 # Number of branches executed +system.cpu.iew.exec_stores 371621620 # Number of stores executed +system.cpu.iew.exec_rate 1.479451 # Inst execution rate +system.cpu.iew.wb_sent 2328619665 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2317593888 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1309821619 # num instructions producing a value +system.cpu.iew.wb_consumers 2336262105 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.456458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.560648 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1004600706 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 45699022 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1407891090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.339134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.034210 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 652274208 46.33% 46.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 388083214 27.56% 73.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 132034153 9.38% 83.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 69283607 4.92% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 48326626 3.43% 91.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18528976 1.32% 92.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23779079 1.69% 94.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7923868 0.56% 95.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67657359 4.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1407891090 # Number of insts commited each cycle +system.cpu.commit.count 1885354147 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 908389591 # Number of memory references committed +system.cpu.commit.loads 631390738 # Number of loads committed +system.cpu.commit.membars 9986 # Number of memory barriers committed +system.cpu.commit.branches 291352101 # Number of branches committed +system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1653713099 # Number of committed integer instructions. +system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.bw_lim_events 67657359 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 4230170239 # The number of ROB reads +system.cpu.rob.rob_writes 5926292122 # The number of ROB writes +system.cpu.timesIdled 1344848 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36993813 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1885343131 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated +system.cpu.cpi 0.844013 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.844013 # CPI: Total CPI of All Threads +system.cpu.ipc 1.184816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.184816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11587728749 # number of integer regfile reads +system.cpu.int_regfile_writes 2306495167 # number of integer regfile writes +system.cpu.fp_regfile_reads 69468418 # number of floating regfile reads +system.cpu.fp_regfile_writes 51554923 # number of floating regfile writes +system.cpu.misc_regfile_reads 3827336094 # number of misc regfile reads +system.cpu.misc_regfile_writes 13780014 # number of misc regfile writes +system.cpu.icache.replacements 25559 # number of replacements +system.cpu.icache.tagsinuse 1546.566470 # Cycle average of tags in use +system.cpu.icache.total_refs 361924025 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 27145 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13332.990422 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1546.566470 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.755159 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 361924028 # number of ReadReq hits +system.cpu.icache.demand_hits 361924028 # number of demand (read+write) hits +system.cpu.icache.overall_hits 361924028 # number of overall hits +system.cpu.icache.ReadReq_misses 27607 # number of ReadReq misses +system.cpu.icache.demand_misses 27607 # number of demand (read+write) misses +system.cpu.icache.overall_misses 27607 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 250013500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 250013500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 250013500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 361951635 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 361951635 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 361951635 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 27622 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 464 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 155969000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000075 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 27158 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 13383.138890 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9056.163292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9056.163292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9056.163292 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 363393229 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9064.622402 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5743.022314 # average overall mshr miss latency -system.cpu.icache.demand_hits 363365607 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 250383000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 27622 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 464 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 155969000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 455 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 455 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 455 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 27152 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 27152 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 27152 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 155884000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 155884000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 155884000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000075 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 27158 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1549.568849 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.756625 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 363393229 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9064.622402 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5743.022314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 363365607 # number of overall hits -system.cpu.icache.overall_miss_latency 250383000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 27622 # number of overall misses -system.cpu.icache.overall_mshr_hits 464 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 155969000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 27158 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 25561 # number of replacements -system.cpu.icache.sampled_refs 27151 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5741.160872 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5741.160872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5741.160872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1549.568849 # Cycle average of tags in use -system.cpu.icache.total_refs 363365604 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37168687 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 49895765 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 348756775 # Number of branches executed -system.cpu.iew.exec_nop 65493 # number of nop insts executed -system.cpu.iew.exec_rate 1.479521 # Inst execution rate -system.cpu.iew.exec_refs 1131335426 # number of memory reference insts executed -system.cpu.iew.exec_stores 371509885 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 17394060 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 927609743 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 231433 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 9066267 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 465231191 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2899637757 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 759825541 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94064084 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2356880983 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2638032 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 300 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 146381913 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 3942741 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 37882384 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 1377639 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 2658197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 296219006 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 188232340 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2658197 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 12410188 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 37485577 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 2331728093 # num instructions consuming a value -system.cpu.iew.wb_count 2317489911 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.562854 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1312422376 # num instructions producing a value -system.cpu.iew.wb_rate 1.454793 # insts written-back per cycle -system.cpu.iew.wb_sent 2328575568 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 11595279326 # number of integer regfile reads -system.cpu.int_regfile_writes 2306970978 # number of integer regfile writes -system.cpu.ipc 1.183515 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.183515 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1196267709 48.81% 48.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11218358 0.46% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 8628 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 49.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 49.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6177350 0.25% 49.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 25435994 1.04% 50.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 793496500 32.38% 83.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 410088765 16.73% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2450945067 # Type of FU issued -system.cpu.iq.fp_alu_accesses 66027207 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 126553287 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 57767686 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 103061655 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 75909773 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.030972 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12391 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23967 0.03% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 52380943 69.00% 69.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23492472 30.95% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 2460827633 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 6419542643 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 2259722225 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 3795271933 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2899328074 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2450945067 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 244190 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 997384206 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12461792 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 32404 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2708929658 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1555834231 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.575325 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.655347 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 573245192 36.84% 36.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 302098178 19.42% 56.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 270294423 17.37% 73.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171510640 11.02% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 147471533 9.48% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 56656397 3.64% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24168420 1.55% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7568098 0.49% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2821350 0.18% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1555834231 # Number of insts issued each cycle -system.cpu.iq.rate 1.538569 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 72720 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.683474 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.187900 # average ReadExReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1531405 # number of replacements +system.cpu.dcache.tagsinuse 4094.850466 # Cycle average of tags in use +system.cpu.dcache.total_refs 980041629 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1535501 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 638.255285 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 325046000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.850466 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 703882480 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 276128743 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 16835 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 13541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 980011223 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 980011223 # number of overall hits +system.cpu.dcache.ReadReq_misses 1932681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 806935 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2739616 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2739616 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 66544329000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28306423000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 94850752000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 94850752000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 705815161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 16838 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 13541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 982750839 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 982750839 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002738 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000178 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.002788 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002788 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 34431.098045 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35078.938204 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34621.914896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34621.914896 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 107019 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 469901 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 734207 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1204108 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1204108 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1462780 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 72728 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1535508 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1535508 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 49902321500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2361229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52263550500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52263550500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.001562 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001562 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34114.714106 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.574084 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34036.651388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34036.651388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 1479610 # number of replacements +system.cpu.l2cache.tagsinuse 31966.303160 # Cycle average of tags in use +system.cpu.l2cache.total_refs 83557 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512330 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.055251 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 28970.488218 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2995.814942 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.884109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.091425 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 75230 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107019 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits 6637 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2279776500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.908732 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 66083 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048651500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 66083 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1489965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34238.898726 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.364741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 75240 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 48438626000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.949502 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1414725 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 43856340000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949488 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1414704 # number of ReadReq MSHR misses +system.cpu.l2cache.demand_hits 81867 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 81867 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1414695 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 66084 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1480779 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1480779 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48470185000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2279814000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50749999000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50749999000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1489925 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 107019 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 7 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_accesses 72721 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1562646 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1562646 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.949508 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 0.714286 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.714286 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107000 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107000 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.055254 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.908733 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.947610 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.947610 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34261.932784 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.728891 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34272.500488 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34272.500488 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1562685 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34250.491961 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.401476 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 81877 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 50718402500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.947605 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1480808 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 45904991500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.947591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1480787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 28973.685280 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2993.152409 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.884207 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.091344 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 1562685 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34250.491961 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.401476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 81877 # number of overall hits -system.cpu.l2cache.overall_miss_latency 50718402500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.947605 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1480808 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 45904991500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.947591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1480787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 66099 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 23 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1414672 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66084 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1480756 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1480756 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1479625 # number of replacements -system.cpu.l2cache.sampled_refs 1512345 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 43855333500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048687000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 45904020500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 45904020500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.714286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908733 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.947595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.947595 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.354499 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.255977 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.394731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.394731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31966.837689 # Cycle average of tags in use -system.cpu.l2cache.total_refs 83563 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.memDep0.conflictingLoads 97040035 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144361648 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 927609743 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 465231191 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 3829379582 # number of misc regfile reads -system.cpu.misc_regfile_writes 13780010 # number of misc regfile writes -system.cpu.numCycles 1593002918 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 25386531 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1993168535 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 3907408 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 760805018 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 7406697 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 15047193383 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 3194680592 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 3359704809 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 606032208 # Number of cycles rename is running -system.cpu.rename.SquashCycles 146381913 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 13958692 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 1366536269 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 653924872 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 14393268511 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 3269869 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 253997 # count of serializing insts renamed -system.cpu.rename.skidInsts 34813344 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 254310 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 4241354068 # The number of ROB reads -system.cpu.rob.rob_writes 5945603467 # The number of ROB writes -system.cpu.timesIdled 1344843 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 1411 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |