diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
| commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
| tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/long/40.perlbmk/ref/arm | |
| parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
| download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz | |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/long/40.perlbmk/ref/arm')
9 files changed, 534 insertions, 511 deletions
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index eb78a5974..08bc6d208 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index cb125c559..742d795a3 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 22 2011 10:22:27 -M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip -M5 started Feb 22 2011 10:32:06 +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:10:23 M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1390,4 +1390,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 1106986295500 because target called exit() +Exiting @ tick 888395700000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index ecc795b7f..ebe1b4a06 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,130 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123409 # Simulator instruction rate (inst/s) -host_mem_usage 261412 # Number of bytes of host memory used -host_seconds 14940.26 # Real time elapsed on the host -host_tick_rate 74094191 # Simulator tick rate (ticks/s) +host_inst_rate 93209 # Simulator instruction rate (inst/s) +host_mem_usage 261176 # Number of bytes of host memory used +host_seconds 20227.01 # Real time elapsed on the host +host_tick_rate 43921255 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1843755906 # Number of instructions simulated -sim_seconds 1.106986 # Number of seconds simulated -sim_ticks 1106986295500 # Number of ticks simulated +sim_insts 1885343196 # Number of instructions simulated +sim_seconds 0.888396 # Number of seconds simulated +sim_ticks 888395700000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 334577290 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 553224059 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 46883846 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 562377080 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 562377080 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 258172659 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 41405243 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 320049862 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 448194519 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 4209077 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 36587037 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 430263617 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 576330823 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 59151677 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 291323462 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 52629133 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 2026424997 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.909862 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.566343 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1586798560 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.188150 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.801160 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 1126460027 55.59% 55.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 528416767 26.08% 81.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 168171926 8.30% 89.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 70727286 3.49% 93.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 47338473 2.34% 95.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 23657956 1.17% 96.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 13792404 0.68% 97.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 6454915 0.32% 97.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 41405243 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 733168598 46.20% 46.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 461552384 29.09% 75.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 183176106 11.54% 86.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 69760651 4.40% 91.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 39275971 2.48% 93.71% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21329022 1.34% 95.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 17961260 1.13% 96.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 7945435 0.50% 96.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 52629133 3.32% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 2026424997 # Number of insts commited each cycle -system.cpu.commit.COM:count 1843766922 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 1586798560 # Number of insts commited each cycle +system.cpu.commit.COM:count 1885354212 # Number of instructions committed system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1619025870 # Number of committed integer instructions. -system.cpu.commit.COM:loads 631405848 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 908401145 # Number of memory references committed +system.cpu.commit.COM:function_calls 41577833 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1660589620 # Number of committed integer instructions. +system.cpu.commit.COM:loads 631390751 # Number of loads committed +system.cpu.commit.COM:membars 9986 # Number of memory barriers committed +system.cpu.commit.COM:refs 908389617 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84212929 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1843766922 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 188261 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1168824477 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1843755906 # Number of Instructions Simulated -system.cpu.committedInsts_total 1843755906 # Number of Instructions Simulated -system.cpu.cpi 1.200795 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.200795 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 714254563 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34305.782527 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34068.836467 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 712322726 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 66273180000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002705 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1931837 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 467831 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 49876981000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002050 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1464006 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 276945664 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35173.008313 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32580.155094 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276142350 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28254970000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002901 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 803314 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 730842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2361149000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000262 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72472 # number of WriteReq MSHR misses +system.cpu.commit.branchMispredicts 42140724 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1885354212 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 211801 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1156399971 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1885343196 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885343196 # Number of Instructions Simulated +system.cpu.cpi 0.942423 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.942423 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 16519 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 36000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 16516 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 108000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 722622865 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34341.472519 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34097.365081 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 720694089 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 66237008000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002669 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1928776 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 466378 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 49863918500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1462398 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 13554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 13554 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 276935679 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 35036.584459 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32455.691504 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 276128738 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28272456500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 806941 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 734201 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2360827000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 72740 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 643.332595 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 13500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 649.359320 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 32000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 991200227 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34560.486788 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33998.618919 # average overall mshr miss latency -system.cpu.dcache.demand_hits 988465076 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94528150000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002759 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2735151 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1198673 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 52238130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001550 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1536478 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 999558544 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34546.506272 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34019.577067 # average overall mshr miss latency +system.cpu.dcache.demand_hits 996822827 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94509464500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002737 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2735717 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1200579 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 52224745500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1535138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999786 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.125005 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 991200227 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34560.486788 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33998.618919 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999736 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.919644 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 999558544 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34546.506272 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34019.577067 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 988465076 # number of overall hits -system.cpu.dcache.overall_miss_latency 94528150000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002759 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2735151 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1198673 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 52238130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001550 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1536478 # number of overall MSHR misses +system.cpu.dcache.overall_hits 996822827 # number of overall hits +system.cpu.dcache.overall_miss_latency 94509464500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002737 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2735717 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1200579 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 52224745500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1535138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1532380 # number of replacements -system.cpu.dcache.sampled_refs 1536476 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1531037 # number of replacements +system.cpu.dcache.sampled_refs 1535133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.125005 # Cycle average of tags in use -system.cpu.dcache.total_refs 988465092 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 341948000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106863 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 223702822 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3748475939 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 853302514 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 949015541 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 187283447 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 404118 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.919644 # Cycle average of tags in use +system.cpu.dcache.total_refs 996852921 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 338455000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107062 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 151107419 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 10897 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 90820701 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 3444690201 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 769283467 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 663881028 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 162526897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 20592 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2526644 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -146,150 +158,150 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 562377080 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 400588374 # Number of cache lines fetched -system.cpu.fetch.Cycles 1002800660 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 11586077 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2972268195 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 34317 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 86966870 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.254013 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 400588374 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 334577290 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.342505 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 2213708442 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.777306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.798612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 576330823 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 375416464 # Number of cache lines fetched +system.cpu.fetch.Cycles 685697881 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 13774150 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2674548145 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 41436 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 45967312 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.324366 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 375416464 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 379201539 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.505269 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1749325455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.017320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.964953 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1213776794 54.83% 54.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 388415258 17.55% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 93122307 4.21% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48895922 2.21% 78.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 60943545 2.75% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76981670 3.48% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 16173405 0.73% 85.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 35829919 1.62% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 279569622 12.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1063664133 60.80% 60.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 45709797 2.61% 63.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 107764294 6.16% 69.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 64274521 3.67% 73.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 89788894 5.13% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63164111 3.61% 82.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32677214 1.87% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 54411477 3.11% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 227871014 13.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2213708442 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 66048246 # number of floating regfile reads -system.cpu.fp_regfile_writes 52282096 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 400588374 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8967.427082 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5871.293987 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 400557689 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 275165500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000077 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 30685 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1813 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 169516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000072 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 28872 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1749325455 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 71543998 # number of floating regfile reads +system.cpu.fp_regfile_writes 49528427 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 375416464 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9589.174687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6216.542791 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 375392982 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 225173000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 23482 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 475 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 143024000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 23007 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 13875.010877 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16320.014868 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 400588374 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8967.427082 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5871.293987 # average overall mshr miss latency -system.cpu.icache.demand_hits 400557689 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 275165500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000077 # miss rate for demand accesses -system.cpu.icache.demand_misses 30685 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1813 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 169516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 28872 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 375416464 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9589.174687 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6216.542791 # average overall mshr miss latency +system.cpu.icache.demand_hits 375392982 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 225173000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses +system.cpu.icache.demand_misses 23482 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 475 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 143024000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 23007 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.814790 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1668.688980 # Average occupied blocks per context -system.cpu.icache.overall_accesses 400588374 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8967.427082 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5871.293987 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.752121 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1540.344515 # Average occupied blocks per context +system.cpu.icache.overall_accesses 375416464 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9589.174687 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6216.542791 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 400557689 # number of overall hits -system.cpu.icache.overall_miss_latency 275165500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000077 # miss rate for overall accesses -system.cpu.icache.overall_misses 30685 # number of overall misses -system.cpu.icache.overall_mshr_hits 1813 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 169516000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 28872 # number of overall MSHR misses +system.cpu.icache.overall_hits 375392982 # number of overall hits +system.cpu.icache.overall_miss_latency 225173000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses +system.cpu.icache.overall_misses 23482 # number of overall misses +system.cpu.icache.overall_mshr_hits 475 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 143024000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 23007 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 27162 # number of replacements -system.cpu.icache.sampled_refs 28869 # Sample count of references to valid blocks. +system.cpu.icache.replacements 21420 # number of replacements +system.cpu.icache.sampled_refs 23002 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1668.688980 # Cycle average of tags in use -system.cpu.icache.total_refs 400557689 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1540.344515 # Cycle average of tags in use +system.cpu.icache.total_refs 375392982 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 264150 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 328211891 # Number of branches executed -system.cpu.iew.EXEC:nop 104784 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.050105 # Inst execution rate -system.cpu.iew.EXEC:refs 1122138306 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 367853547 # Number of stores executed +system.cpu.idleCycles 27465946 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 359805156 # Number of branches executed +system.cpu.iew.EXEC:nop 99005 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.327116 # Inst execution rate +system.cpu.iew.EXEC:refs 1136161492 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 370067841 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2149736970 # num instructions consuming a value -system.cpu.iew.WB:count 2244737126 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.548413 # average fanout of values written-back +system.cpu.iew.WB:consumers 2411359497 # num instructions consuming a value +system.cpu.iew.WB:count 2310892149 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.529668 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1178943946 # num instructions producing a value -system.cpu.iew.WB:rate 1.013896 # insts written-back per cycle -system.cpu.iew.WB:sent 2266943895 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 93876953 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4821399 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 976823889 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 9835077 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 65011197 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 487070109 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3012606198 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 754284759 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 120224771 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2324903771 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 971459 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1277221062 # num instructions producing a value +system.cpu.iew.WB:rate 1.300598 # insts written-back per cycle +system.cpu.iew.WB:sent 2315816685 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 45692986 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 17451585 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 932904384 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 231723 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 12876854 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 478323402 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3041768804 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 766093651 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 62095934 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2358008462 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1124743 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 242 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 187283447 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1560865 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 162526897 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2446641 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 12454380 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 31009134 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1377501 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 2755264 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1382 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 345418040 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 210074812 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2755264 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 45729465 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 48147488 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 5403649891 # number of integer regfile reads -system.cpu.int_regfile_writes 1668305360 # number of integer regfile writes -system.cpu.ipc 0.832782 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.832782 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 4866291 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 301513632 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 201324536 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 4866291 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 7718452 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37974534 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5503137315 # number of integer regfile reads +system.cpu.int_regfile_writes 1718781055 # number of integer regfile writes +system.cpu.ipc 1.061094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.061094 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1195859034 48.91% 48.91% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 11168379 0.46% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 16846 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1183656160 48.91% 48.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 11225256 0.46% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8912 0.00% 49.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.37% # Type of FU issued @@ -300,89 +312,89 @@ system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.37% # system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 49.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876473 0.28% 49.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501179 0.22% 49.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23390230 0.96% 50.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 793077280 32.43% 83.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 407863832 16.68% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 49.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876473 0.28% 49.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501174 0.23% 49.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385813 0.97% 50.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 791490934 32.70% 83.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 396584385 16.39% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2445128542 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 60724253 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024835 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2420104396 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 57562117 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.023785 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 336 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.04% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 44167441 72.73% 72.77% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 16532363 27.23% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 17939 0.03% 0.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.04% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 45310366 78.72% 78.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 12209699 21.21% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 2213708442 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.104540 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.422226 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1749325455 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.383450 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.501844 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 1044209874 47.17% 47.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 536089548 24.22% 71.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 282659967 12.77% 84.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 162995448 7.36% 91.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 122130271 5.52% 97.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 40278652 1.82% 98.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 15378668 0.69% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 7181748 0.32% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2784266 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 679087816 38.82% 38.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 375608779 21.47% 60.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 324177593 18.53% 78.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 189762671 10.85% 89.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 109320419 6.25% 95.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 45946515 2.63% 98.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 20912326 1.20% 99.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1710477 0.10% 99.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2798859 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 2213708442 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.104408 # Inst issue rate -system.cpu.iq.fp_alu_accesses 64689412 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 126628637 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 56420382 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 101846831 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 2441163383 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 7046405646 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 2188316744 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 4055199620 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 3002666337 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2445128542 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 9835077 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1141792420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 8344504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 9646816 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2082844826 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1749325455 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.362064 # Inst issue rate +system.cpu.iq.fp_alu_accesses 63302900 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 122479905 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 59166670 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 79315867 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2414363613 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 6524640046 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2251725479 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 4122242728 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 3041425729 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2420104396 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 244070 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1156073456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 32269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1931732931 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -404,114 +416,115 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 72470 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.335527 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.225657 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 6383 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2279891500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.911922 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 66087 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048778000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.911922 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 66087 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1492876 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34237.383587 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.264277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 77656 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 48453430000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.947982 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1415220 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 43870985000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.947956 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1415181 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.554826 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.104688 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 6653 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2279733500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.908531 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048615000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1485400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34238.677361 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.325576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 70955 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 48428726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.952232 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1414445 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 43847418500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.952214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1414418 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 5 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106863 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106863 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107062 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107062 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.056843 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.052436 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1565346 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34249.025692 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 84039 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 50733321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.946313 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1481307 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 45919763000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.946288 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1481268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 1558135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34250.276760 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.360351 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 77608 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 50708459500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.950192 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1480527 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 45896033500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.950174 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1480500 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.884785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.091201 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 28992.645122 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2988.461105 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1565346 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34249.025692 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.884303 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.091380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28976.831350 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2994.327644 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1558135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34250.276760 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.360351 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 84039 # number of overall hits -system.cpu.l2cache.overall_miss_latency 50733321500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.946313 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1481307 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 39 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 45919763000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.946288 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1481268 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 77608 # number of overall hits +system.cpu.l2cache.overall_miss_latency 50708459500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.950192 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1480527 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 45896033500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.950174 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1480500 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1479999 # number of replacements -system.cpu.l2cache.sampled_refs 1512721 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1479411 # number of replacements +system.cpu.l2cache.sampled_refs 1512131 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31981.106227 # Cycle average of tags in use -system.cpu.l2cache.total_refs 85987 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31971.158994 # Cycle average of tags in use +system.cpu.l2cache.total_refs 79290 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.memDep0.conflictingLoads 48375882 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 976823889 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 487070109 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 4207984130 # number of misc regfile reads -system.cpu.misc_regfile_writes 14227476 # number of misc regfile writes -system.cpu.numCycles 2213972592 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 103195431 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 198192590 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 932904384 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 478323402 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 3956756575 # number of misc regfile reads +system.cpu.misc_regfile_writes 14227477 # number of misc regfile writes +system.cpu.numCycles 1776791401 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 919120364 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8406320 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 9255846828 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3353421825 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2685986515 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 880460594 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 187283447 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 23975324 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1203659004 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 485863672 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 8769983156 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 185210219 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 226114384 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 13965392 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 4997592808 # The number of ROB reads -system.cpu.rob.rob_writes 6212468368 # The number of ROB writes -system.cpu.timesIdled 87017 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 26318091 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1523914797 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 14245310 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 796885476 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 9677436 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 9044956904 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3344057735 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2666278058 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 638477320 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 162526897 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 33719663 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1142363258 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 419453355 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 8625503549 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 91398008 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 8495416 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 83627358 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 245009 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 4575905265 # The number of ROB reads +system.cpu.rob.rob_writes 6246035428 # The number of ROB writes +system.cpu.timesIdled 1346500 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 97cb6c6e4..161aadfee 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -66,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout index e6fdba858..467c19c32 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:24 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:44:47 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1390,4 +1390,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 924828408500 because target called exit() +Exiting @ tick 945613131000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 807917422..b4eaa4e1c 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 966272 # Simulator instruction rate (inst/s) -host_mem_usage 234680 # Number of bytes of host memory used -host_seconds 1908.12 # Real time elapsed on the host -host_tick_rate 484679459 # Simulator tick rate (ticks/s) +host_inst_rate 1687648 # Simulator instruction rate (inst/s) +host_mem_usage 251592 # Number of bytes of host memory used +host_seconds 1117.14 # Real time elapsed on the host +host_tick_rate 846460115 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1843766922 # Number of instructions simulated -sim_seconds 0.924828 # Number of seconds simulated -sim_ticks 924828408500 # Number of ticks simulated +sim_insts 1885336367 # Number of instructions simulated +sim_seconds 0.945613 # Number of seconds simulated +sim_ticks 945613131000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1849656818 # number of cpu cycles simulated +system.cpu.numCycles 1891226263 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1849656818 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 1891226263 # Number of busy cycles +system.cpu.num_conditional_control_insts 223597262 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 84508263 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1843766922 # Number of instructions executed -system.cpu.num_int_alu_accesses 1619025871 # Number of integer alu accesses -system.cpu.num_int_insts 1619025871 # number of integer instructions -system.cpu.num_int_register_reads 4830749754 # number of times the integer registers were read -system.cpu.num_int_register_writes 1365217022 # number of times the integer registers were written -system.cpu.num_load_insts 631405848 # Number of load instructions -system.cpu.num_mem_refs 908401146 # number of memory refs +system.cpu.num_insts 1885336367 # Number of instructions executed +system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses +system.cpu.num_int_insts 1660575345 # number of integer instructions +system.cpu.num_int_register_reads 4913858688 # number of times the integer registers were read +system.cpu.num_int_register_writes 1405410845 # number of times the integer registers were written +system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index dfd8de545..734b01f7e 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 @@ -166,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index b556adbf3..871cc997a 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:25 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:10:25 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1390,4 +1390,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2369896178000 because target called exit() +Exiting @ tick 2369901960000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 1e3225702..ae9492554 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,27 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 494422 # Simulator instruction rate (inst/s) -host_mem_usage 242392 # Number of bytes of host memory used -host_seconds 3706.70 # Real time elapsed on the host -host_tick_rate 639353926 # Simulator tick rate (ticks/s) +host_inst_rate 678497 # Simulator instruction rate (inst/s) +host_mem_usage 259312 # Number of bytes of host memory used +host_seconds 2762.35 # Real time elapsed on the host +host_tick_rate 857930242 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1832675505 # Number of instructions simulated -sim_seconds 2.369896 # Number of seconds simulated -sim_ticks 2369896178000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 54567.414542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51567.414542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 79731778000 # number of ReadReq miss cycles +sim_insts 1874244950 # Number of instructions simulated +sim_seconds 2.369902 # Number of seconds simulated +sim_ticks 2369901960000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75348295000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276872883 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses @@ -30,48 +34,48 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # m system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54452.292494 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency -system.cpu.dcache.demand_hits 895775787 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 83526604000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1533941 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 78924781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1533941 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999748 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.966269 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54452.292494 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999746 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 895775787 # number of overall hits -system.cpu.dcache.overall_miss_latency 83526604000 # number of overall miss cycles +system.cpu.dcache.overall_hits 895737439 # number of overall hits +system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1533941 # number of overall misses +system.cpu.dcache.overall_misses 1533653 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 78924781000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1533941 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1529845 # number of replacements -system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1529557 # number of replacements +system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.966269 # Cycle average of tags in use -system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 993944000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107259 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 1390241555 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1390221752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses @@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # ms system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 70202.583043 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1390241555 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency -system.cpu.icache.demand_hits 1390221752 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses @@ -127,12 +131,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1392.325384 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1390221752 # number of overall hits +system.cpu.icache.overall_hits 1390251708 # number of overall hits system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses system.cpu.icache.overall_misses 19803 # number of overall misses @@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 18364 # number of replacements system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1392.325384 # Cycle average of tags in use -system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use +system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses 66093 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 67385 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 73506108000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.954499 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1413579 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56543160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954499 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1413579 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.050081 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 74072 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 76942944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.952327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1479672 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 59186880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.952327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1479672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881760 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.092816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 28893.501877 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3041.393075 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.881757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.092817 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 74072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 76942944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.952327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1479672 # number of overall misses +system.cpu.l2cache.overall_hits 73826 # number of overall hits +system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1479630 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 59186880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.952327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1479672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1478797 # number of replacements -system.cpu.l2cache.sampled_refs 1511517 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1478755 # number of replacements +system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31934.894953 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75699 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use +system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66099 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4739792356 # number of cpu cycles simulated +system.cpu.numCycles 4739803920 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 4739792356 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 4739803920 # Number of busy cycles +system.cpu.num_conditional_control_insts 223597262 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 84508263 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1832675505 # Number of instructions executed -system.cpu.num_int_alu_accesses 1619025871 # Number of integer alu accesses -system.cpu.num_int_insts 1619025871 # number of integer instructions -system.cpu.num_int_register_reads 5455211671 # number of times the integer registers were read -system.cpu.num_int_register_writes 1365288731 # number of times the integer registers were written -system.cpu.num_load_insts 631405848 # Number of load instructions -system.cpu.num_mem_refs 908401146 # number of memory refs +system.cpu.num_insts 1874244950 # Number of instructions executed +system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses +system.cpu.num_int_insts 1660575345 # number of integer instructions +system.cpu.num_int_register_reads 5538311924 # number of times the integer registers were read +system.cpu.num_int_register_writes 1405482554 # number of times the integer registers were written +system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls |