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authorKevin Lim <ktlim@umich.edu>2007-04-27 14:35:58 -0400
committerKevin Lim <ktlim@umich.edu>2007-04-27 14:35:58 -0400
commit7f39291c81cb65dc166926136c8f3cab253df160 (patch)
tree8e2ef8eb5b3d3a092025a2a390be07cfc2e3c25b /tests/long/40.perlbmk/ref
parent522e59840f2d3c44d7d95ebc44b44abebb1212c9 (diff)
downloadgem5-7f39291c81cb65dc166926136c8f3cab253df160.tar.xz
Update Alpha reference stats for clock changes.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out: tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out: tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr: Update refs for clock changes. --HG-- extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
Diffstat (limited to 'tests/long/40.perlbmk/ref')
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini34
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out31
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt12
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr3
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini34
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out31
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt122
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr3
8 files changed, 87 insertions, 183 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 59c6e25e2..dc1116a7e 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,33 +1,7 @@
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
@@ -38,7 +12,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
-clock=1
+clock=500
cpu_id=0
defer_registration=false
function_trace=false
@@ -59,11 +33,11 @@ icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
egid=100
env=
euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
output=cout
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
index c6e4aa136..ef449bf6d 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
@@ -1,9 +1,6 @@
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
@@ -27,11 +24,11 @@ responder_set=false
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
system=system
uid=100
euid=100
@@ -50,7 +47,7 @@ progress_interval=0
system=system
cpu_id=0
workload=system.cpu.workload
-clock=1
+clock=500
phase=0
defer_registration=false
width=1
@@ -58,23 +55,3 @@ function_trace=false
function_trace_start=0
simulate_stalls=false
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
index 9db3f64bc..5fa1b5726 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1149393 # Simulator instruction rate (inst/s)
-host_mem_usage 177516 # Number of bytes of host memory used
-host_seconds 1747.87 # Real time elapsed on the host
-host_tick_rate 1149393 # Simulator tick rate (ticks/s)
+host_inst_rate 855453 # Simulator instruction rate (inst/s)
+host_mem_usage 151192 # Number of bytes of host memory used
+host_seconds 2348.45 # Real time elapsed on the host
+host_tick_rate 427726617 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
-sim_seconds 0.002009 # Number of seconds simulated
-sim_ticks 2008987606 # Number of ticks simulated
+sim_seconds 1.004494 # Number of seconds simulated
+sim_ticks 1004493803000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2008987607 # number of cpu cycles simulated
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
index bc72461c8..a6133a5ee 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
@@ -1,3 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 5f64dcebd..6f1f78d48 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -1,33 +1,7 @@
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
@@ -38,7 +12,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
cpu_id=0
defer_registration=false
function_trace=false
@@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
output=cout
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
index 6998f4828..1c3b86ae3 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
@@ -1,9 +1,6 @@
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
@@ -27,11 +24,11 @@ responder_set=false
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
system=system
uid=100
euid=100
@@ -50,7 +47,7 @@ progress_interval=0
system=system
cpu_id=0
workload=system.cpu.workload
-clock=1
+clock=500
phase=0
defer_registration=false
// width not specified
@@ -179,23 +176,3 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
index 45f793ab7..afc2c695a 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,35 +1,35 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 752631 # Simulator instruction rate (inst/s)
-host_mem_usage 230876 # Number of bytes of host memory used
-host_seconds 2669.29 # Real time elapsed on the host
-host_tick_rate 2836913 # Simulator tick rate (ticks/s)
+host_inst_rate 594701 # Simulator instruction rate (inst/s)
+host_mem_usage 156660 # Number of bytes of host memory used
+host_seconds 3378.14 # Real time elapsed on the host
+host_tick_rate 405574512 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
-sim_seconds 0.007573 # Number of seconds simulated
-sim_ticks 7572532003 # Number of ticks simulated
+sim_seconds 1.370090 # Number of seconds simulated
+sim_ticks 1370089513500 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 720334778 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1530144 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2008977012 # number of overall hits
-system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_misses 10596 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
@@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.014399 # mi
system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
@@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 107393 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1507936 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 1474094 # number of replacements
system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use
system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66804 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 7572532003 # number of cpu cycles simulated
+system.cpu.numCycles 1370089513500 # number of cpu cycles simulated
system.cpu.num_insts 2008987607 # Number of instructions executed
system.cpu.num_refs 722390435 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
index bc72461c8..a6133a5ee 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
@@ -1,3 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: Increasing stack size by one page.