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authorAli Saidi <saidi@eecs.umich.edu>2007-05-15 19:25:35 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-05-15 19:25:35 -0400
commitb85690e239616b703881b7734b0559f61f9eb75e (patch)
treef144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/long/40.perlbmk
parentc30e615689148c6e5ecd06e86069cba716dec5e0 (diff)
downloadgem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz
update all the regresstion tests for release
--HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/long/40.perlbmk')
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini1
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out1
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt8
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini11
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out11
-rw-r--r--tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt104
6 files changed, 68 insertions, 68 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index dc1116a7e..1b858fca2 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
index ef449bf6d..0e4ea1cb5 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=LiveProcess
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
index 5fa1b5726..0f58a9003 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 855453 # Simulator instruction rate (inst/s)
-host_mem_usage 151192 # Number of bytes of host memory used
-host_seconds 2348.45 # Real time elapsed on the host
-host_tick_rate 427726617 # Simulator tick rate (ticks/s)
+host_inst_rate 855891 # Simulator instruction rate (inst/s)
+host_mem_usage 151228 # Number of bytes of host memory used
+host_seconds 2347.25 # Real time elapsed on the host
+host_tick_rate 427945543 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
sim_seconds 1.004494 # Number of seconds simulated
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 6f1f78d48..dd36bbf60 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=10000
lifo=false
max_miss_count=0
mshrs=10
@@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
@@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
index 1c3b86ae3..676b65128 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=LiveProcess
@@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
-latency=1
+latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
index afc2c695a..6aa1ee5aa 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 594701 # Simulator instruction rate (inst/s)
-host_mem_usage 156660 # Number of bytes of host memory used
-host_seconds 3378.14 # Real time elapsed on the host
-host_tick_rate 405574512 # Simulator tick rate (ticks/s)
+host_inst_rate 622738 # Simulator instruction rate (inst/s)
+host_mem_usage 156744 # Number of bytes of host memory used
+host_seconds 3226.05 # Real time elapsed on the host
+host_tick_rate 852686846 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
-sim_seconds 1.370090 # Number of seconds simulated
-sim_ticks 1370089513500 # Number of ticks simulated
+sim_seconds 2.750814 # Number of seconds simulated
+sim_ticks 2750814393000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 20372446000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 18914254000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 998252000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 926300000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 13966.461980 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 21370698000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 19840554000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 13966.461980 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 720334778 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 21370698000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1530144 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 19840554000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.422371 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 702832000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 12448.659872 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 131906000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 121310000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 12448.659872 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 131906000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 121310000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 12448.659872 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2008977012 # number of overall hits
-system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 131906000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_misses 10596 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 121310000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1478.610505 # Cycle average of tags in use
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 19589206000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 16575482000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
@@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 19589206000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 16575482000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 12990.740986 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 107393 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 19589206000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1507936 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 16575482000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 1474094 # number of replacements
system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 32753.638584 # Cycle average of tags in use
system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle 2394479000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66804 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1370089513500 # number of cpu cycles simulated
+system.cpu.numCycles 2750814393000 # number of cpu cycles simulated
system.cpu.num_insts 2008987607 # Number of instructions executed
system.cpu.num_refs 722390435 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls