diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/40.perlbmk | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/40.perlbmk')
9 files changed, 504 insertions, 535 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 74dda4fbe..eac5f120d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index e4a42f3b8..3c7b7367e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:01:20 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:48:50 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1392,4 +1390,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 702688811500 because target called exit() +Exiting @ tick 702197148500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 75ed9ac65..24cbff05f 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,295 +1,295 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 105247 # Simulator instruction rate (inst/s) -host_mem_usage 214344 # Number of bytes of host memory used -host_seconds 17321.56 # Real time elapsed on the host -host_tick_rate 40567294 # Simulator tick rate (ticks/s) +host_inst_rate 211797 # Simulator instruction rate (inst/s) +host_mem_usage 200548 # Number of bytes of host memory used +host_seconds 8607.50 # Real time elapsed on the host +host_tick_rate 81579716 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated -sim_seconds 0.702689 # Number of seconds simulated -sim_ticks 702688811500 # Number of ticks simulated +sim_seconds 0.702197 # Number of seconds simulated +sim_ticks 702197148500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 239396241 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 292393914 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 3599 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 28358143 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 232710596 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 347019771 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 49329086 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 239361289 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 292350506 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 817 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 28355767 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 232672074 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 346972918 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 49326443 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 67430429 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 67076252 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1305107182 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.539328 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.193562 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1304193061 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.540407 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.191824 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 596079504 45.67% 45.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 274005611 20.99% 66.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 176024939 13.49% 80.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 67867193 5.20% 85.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 46132467 3.53% 88.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 33942844 2.60% 91.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 19726349 1.51% 93.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 23897846 1.83% 94.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 67430429 5.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 594441372 45.58% 45.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 274309752 21.03% 66.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 176336103 13.52% 80.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 68165188 5.23% 85.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 46116026 3.54% 88.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 34003883 2.61% 91.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 19794848 1.52% 93.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 23949637 1.84% 94.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 67076252 5.14% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1305107182 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1304193061 # Number of insts commited each cycle system.cpu.commit.COM:count 2008987604 # Number of instructions committed system.cpu.commit.COM:loads 511595302 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 722390433 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 28346322 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 28343948 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 694586134 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 694286197 # The number of squashed insts skipped by commit system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.770896 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.770896 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 463358852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37466.685698 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34710.185206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 461425148 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 72449480000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004173 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1933704 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 474303 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 50656079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1459401 # number of ReadReq MSHR misses +system.cpu.cpi 0.770357 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.770357 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 463422916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37046.413098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34119.469160 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 461494441 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 71443081500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004161 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1928475 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 469203 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 49789586000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1459272 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38589.512736 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.349360 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210236618 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21543675991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002648 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 558278 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 484005 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2712773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74273 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 37873.224315 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34361.981856 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210247567 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20729113991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 547329 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 475679 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2462036000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71650 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs 6041.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 438.700297 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 438.782653 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 72500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 674153748 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37718.232311 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency -system.cpu.dcache.demand_hits 671661766 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93993155991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003696 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2491982 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 958308 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 53368852000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002275 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1533674 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 674217812 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37229.197259 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency +system.cpu.dcache.demand_hits 671742008 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 92172195491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003672 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2475804 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 944882 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 52251622000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002271 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1530922 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.104320 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 674153748 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37718.232311 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4095.103693 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 674217812 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37229.197259 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 671661766 # number of overall hits -system.cpu.dcache.overall_miss_latency 93993155991 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003696 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2491982 # number of overall misses -system.cpu.dcache.overall_mshr_hits 958308 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 53368852000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002275 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1533674 # number of overall MSHR misses +system.cpu.dcache.overall_hits 671742008 # number of overall hits +system.cpu.dcache.overall_miss_latency 92172195491 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003672 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2475804 # number of overall misses +system.cpu.dcache.overall_mshr_hits 944882 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 52251622000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002271 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1530922 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1526954 # number of replacements -system.cpu.dcache.sampled_refs 1531050 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526826 # number of replacements +system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.104320 # Cycle average of tags in use -system.cpu.dcache.total_refs 671672090 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4095.103693 # Cycle average of tags in use +system.cpu.dcache.total_refs 671742017 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74616 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 31207203 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12052 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 30419221 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2934529925 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 711825403 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561989361 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 100109049 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45710 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 85215 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 772921338 # DTB accesses +system.cpu.dcache.writebacks 107349 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 30546765 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 11879 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30415983 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2934070840 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 711662273 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 561899990 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 100055757 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45705 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 84033 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 772892535 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 772287215 # DTB hits -system.cpu.dtb.data_misses 634123 # DTB misses +system.cpu.dtb.data_hits 772261224 # DTB hits +system.cpu.dtb.data_misses 631311 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 514592222 # DTB read accesses +system.cpu.dtb.read_accesses 514571381 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 513995856 # DTB read hits -system.cpu.dtb.read_misses 596366 # DTB read misses -system.cpu.dtb.write_accesses 258329116 # DTB write accesses +system.cpu.dtb.read_hits 513977951 # DTB read hits +system.cpu.dtb.read_misses 593430 # DTB read misses +system.cpu.dtb.write_accesses 258321154 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258291359 # DTB write hits -system.cpu.dtb.write_misses 37757 # DTB write misses -system.cpu.fetch.Branches 347019771 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 347236210 # Number of cache lines fetched -system.cpu.fetch.Cycles 925540339 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 4572630 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3016868050 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 28795074 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.246923 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 347236210 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 288725327 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.146660 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1405216231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.146907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.027321 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 258283273 # DTB write hits +system.cpu.dtb.write_misses 37881 # DTB write misses +system.cpu.fetch.Branches 346972918 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 347200626 # Number of cache lines fetched +system.cpu.fetch.Cycles 925414333 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4548226 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3016464690 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28792576 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247062 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 347200626 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 288687732 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.147876 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1404248818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.148098 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.027750 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 826912311 58.85% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 54085812 3.85% 62.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 40125133 2.86% 65.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 63577185 4.52% 70.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 121409089 8.64% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34600240 2.46% 81.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37932193 2.70% 83.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7024441 0.50% 84.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 219549827 15.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 826035319 58.82% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 54061013 3.85% 62.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 40121660 2.86% 65.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 63576700 4.53% 70.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 121382183 8.64% 78.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 34599008 2.46% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37926839 2.70% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7023317 0.50% 84.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 219522779 15.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1405216231 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 347236210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15852.092893 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.295350 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 347225531 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 169284500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1404248818 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 347200626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15854.453498 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.008587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 347189949 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 169278000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10679 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 894 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 113959000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10677 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 895 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113843000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 9785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 9782 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 35489.118050 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 35496.365300 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 347236210 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15852.092893 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency -system.cpu.icache.demand_hits 347225531 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 169284500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 347200626 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15854.453498 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency +system.cpu.icache.demand_hits 347189949 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 169278000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_misses 10679 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 894 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 113959000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 10677 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 895 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113843000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 9785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 9782 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.787162 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1612.107078 # Average occupied blocks per context -system.cpu.icache.overall_accesses 347236210 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15852.092893 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.787157 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1612.097956 # Average occupied blocks per context +system.cpu.icache.overall_accesses 347200626 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15854.453498 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 347225531 # number of overall hits -system.cpu.icache.overall_miss_latency 169284500 # number of overall miss cycles +system.cpu.icache.overall_hits 347189949 # number of overall hits +system.cpu.icache.overall_miss_latency 169278000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_misses 10679 # number of overall misses -system.cpu.icache.overall_mshr_hits 894 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 113959000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 10677 # number of overall misses +system.cpu.icache.overall_mshr_hits 895 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113843000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 9785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 9782 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8113 # number of replacements -system.cpu.icache.sampled_refs 9784 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8111 # number of replacements +system.cpu.icache.sampled_refs 9781 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1612.107078 # Cycle average of tags in use -system.cpu.icache.total_refs 347225531 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1612.097956 # Cycle average of tags in use +system.cpu.icache.total_refs 347189949 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 161393 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274718833 # Number of branches executed -system.cpu.iew.EXEC:nop 329034713 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.424505 # Inst execution rate -system.cpu.iew.EXEC:refs 773457001 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258330075 # Number of stores executed +system.cpu.idleCycles 145480 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 274684945 # Number of branches executed +system.cpu.iew.EXEC:nop 329038670 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.425383 # Inst execution rate +system.cpu.iew.EXEC:refs 773428063 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258322146 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1632862772 # num instructions consuming a value -system.cpu.iew.WB:count 2000954749 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.695811 # average fanout of values written-back +system.cpu.iew.WB:consumers 1632528882 # num instructions consuming a value +system.cpu.iew.WB:count 2000778402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.695828 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1136164328 # num instructions producing a value -system.cpu.iew.WB:rate 1.423784 # insts written-back per cycle -system.cpu.iew.WB:sent 2001905607 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 30878599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3451748 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655963109 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 64 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 51733 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 302851236 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2713712461 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 515126926 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 84126603 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2001967300 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 131046 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1135959868 # num instructions producing a value +system.cpu.iew.WB:rate 1.424656 # insts written-back per cycle +system.cpu.iew.WB:sent 2001740023 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 30875630 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3371474 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 655915316 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 69 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 46568 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 302840686 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2713549765 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 515105917 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 84189444 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2001799378 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 130178 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1380 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 100109049 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 140868 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 1349 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 100055757 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 139189 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 50632865 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 227 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 50550937 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 225 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3782 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 4125 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144367807 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 92056105 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3782 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 787958 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30090641 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.297191 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.297191 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 3543 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4083 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 144320014 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92045555 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3543 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 788016 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30087614 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.298099 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.298099 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203926458 57.71% 57.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 17656 0.00% 57.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203839026 57.71% 57.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 18400 0.00% 57.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851408 1.34% 59.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254704 0.40% 59.44% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850839 1.34% 59.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254698 0.40% 59.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204647 0.35% 59.79% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 555703221 26.64% 86.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 283133054 13.57% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 555691648 26.64% 86.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 283126808 13.57% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2086093903 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 35524455 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017029 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2085988822 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 36673966 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017581 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5029 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5496 0.01% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available @@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 26764066 75.34% 75.35% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 8755360 24.65% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 27909398 76.10% 76.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 8759072 23.88% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1405216231 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.484536 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637275 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1404248818 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.485484 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.638010 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 532926303 37.92% 37.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 283749414 20.19% 58.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 275573113 19.61% 77.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 156459284 11.13% 88.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 63140415 4.49% 93.36% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 47210297 3.36% 96.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 32913048 2.34% 99.06% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 10225878 0.73% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 3018479 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 532242124 37.90% 37.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 283422756 20.18% 58.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 275702525 19.63% 77.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 156569721 11.15% 88.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 62891882 4.48% 93.35% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 46986104 3.35% 96.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 33054153 2.35% 99.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 10407537 0.74% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2972016 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1405216231 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.484365 # Inst issue rate -system.cpu.iq.iqInstsAdded 2384677684 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2086093903 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 561606840 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12399741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 517624785 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1404248818 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.485330 # Inst issue rate +system.cpu.iq.iqInstsAdded 2384511026 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2085988822 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 561440182 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12400568 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 517571269 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 347236419 # ITB accesses +system.cpu.itb.fetch_accesses 347200834 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 347236210 # ITB hits -system.cpu.itb.fetch_misses 209 # ITB misses +system.cpu.itb.fetch_hits 347200626 # ITB hits +system.cpu.itb.fetch_misses 208 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,98 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 71649 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 35091.445798 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.513824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2514267000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 71649 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297462000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 71649 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1469186 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34207.393582 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.426347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 29045 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 49263470000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.980231 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1440141 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44644985000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980231 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1440141 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2624 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34296.875000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.905488 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 89995000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2624 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 81349000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2624 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35152.205453 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32141.578294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2350171000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.933105 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66857 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148889500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66857 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1469054 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34210.498210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.429333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 55232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 48367555000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.962403 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1413822 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 43829089000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962403 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1413822 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107349 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107349 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.023753 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.041538 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540835 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34249.291899 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 29045 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 51777737000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981150 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1511790 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 1540704 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34253.019054 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 60025 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 50717726000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.961041 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1480679 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 46942447000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1511790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 45977978500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.961041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1480679 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.927958 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.046323 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 30407.323461 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1517.897239 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1540835 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34249.291899 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.881669 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.093123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28890.531626 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3051.454384 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1540704 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34253.019054 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 29045 # number of overall hits -system.cpu.l2cache.overall_miss_latency 51777737000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981150 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1511790 # number of overall misses +system.cpu.l2cache.overall_hits 60025 # number of overall hits +system.cpu.l2cache.overall_miss_latency 50717726000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.961041 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1480679 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 46942447000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1511790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 45977978500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.961041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1480679 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1474292 # number of replacements -system.cpu.l2cache.sampled_refs 1506959 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1480409 # number of replacements +system.cpu.l2cache.sampled_refs 1513096 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31925.220700 # Cycle average of tags in use -system.cpu.l2cache.total_refs 35795 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31941.986010 # Cycle average of tags in use +system.cpu.l2cache.total_refs 62851 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66899 # number of writebacks -system.cpu.memDep0.conflictingLoads 126385471 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12290638 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 655963109 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 302851236 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1405377624 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 20016233 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 66898 # number of writebacks +system.cpu.memDep0.conflictingLoads 122494554 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20280761 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 655915316 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 302840686 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1404394298 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 19598244 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 673555 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 725805122 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 10749358 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3307765426 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2838518766 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1890285688 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 546657671 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 100109049 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 12606278 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 505316618 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 21878 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2883 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 26993135 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 69 # count of temporary serializing insts renamed -system.cpu.timesIdled 4180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 671773 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 725577995 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 10516920 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 17 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3307285723 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2838114179 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1889955714 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 546658925 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 100055757 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 12336225 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 504986644 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 21672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2827 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 26425102 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 76 # count of temporary serializing insts renamed +system.cpu.timesIdled 3680 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 1ed5d3e81..9457f21b2 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 384b357fd..c8bf5015e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:14 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:48:17 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1392,4 +1390,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2814926000000 because target called exit() +Exiting @ tick 2813467842000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index bd497ee51..21606e309 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1265087 # Simulator instruction rate (inst/s) -host_mem_usage 213100 # Number of bytes of host memory used -host_seconds 1588.02 # Real time elapsed on the host -host_tick_rate 1772597573 # Simulator tick rate (ticks/s) +host_inst_rate 1340007 # Simulator instruction rate (inst/s) +host_mem_usage 199308 # Number of bytes of host memory used +host_seconds 1499.24 # Real time elapsed on the host +host_tick_rate 1876600376 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated -sim_seconds 2.814926 # Number of seconds simulated -sim_ticks 2814926000000 # Number of ticks simulated +sim_seconds 2.813468 # Number of seconds simulated +sim_ticks 2813467842000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55392.203496 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.203496 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 80772468000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 79658418000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 76397892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 75283842000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210720566 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4162480000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000353 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 74330 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3939490000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74330 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3815994000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55421.682690 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency -system.cpu.dcache.demand_hits 720332400 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 84934948000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002123 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1532522 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 54553.304787 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency +system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 83474412000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 80337382000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1532522 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 78883980000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.205038 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55421.682690 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 720332400 # number of overall hits -system.cpu.dcache.overall_miss_latency 84934948000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002123 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1532522 # number of overall misses +system.cpu.dcache.overall_hits 720334778 # number of overall hits +system.cpu.dcache.overall_miss_latency 83474412000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 80337382000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1532522 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 78883980000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.205038 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74616 # number of writebacks +system.cpu.dcache.writebacks 107612 # number of writebacks system.cpu.dtb.data_accesses 722298387 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 721864922 # DTB hits @@ -122,7 +122,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1478.422015 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.422015 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,36 +164,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 5079 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 29321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 74852284000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.980037 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1439467 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 57578680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980037 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1439467 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2378 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 123656000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2378 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 95120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2378 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 55846 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107612 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.023963 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 29321 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 78593788000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1511419 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 60456760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1511419 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.927128 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.046829 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 30380.118149 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1534.487101 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 29321 # number of overall hits -system.cpu.l2cache.overall_miss_latency 78593788000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1511419 # number of overall misses +system.cpu.l2cache.overall_hits 60925 # number of overall hits +system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1479815 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 60456760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1511419 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1473631 # number of replacements -system.cpu.l2cache.sampled_refs 1506296 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1479797 # number of replacements +system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31914.605250 # Cycle average of tags in use -system.cpu.l2cache.total_refs 36095 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use +system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66899 # number of writebacks +system.cpu.l2cache.writebacks 66898 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5629852000 # number of cpu cycles simulated +system.cpu.numCycles 5626935684 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 3cf240e1d..5d6a2ea44 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index 8e18e8ced..6d3d29284 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:52:30 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 14:03:19 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:06:09 +M5 executing on phenom command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1392,4 +1390,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2371349716000 because target called exit() +Exiting @ tick 2369896178000 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index be056051b..bc599ef4c 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1110314 # Simulator instruction rate (inst/s) -host_mem_usage 216744 # Number of bytes of host memory used -host_seconds 1650.59 # Real time elapsed on the host -host_tick_rate 1436666087 # Simulator tick rate (ticks/s) +host_inst_rate 1326917 # Simulator instruction rate (inst/s) +host_mem_usage 202424 # Number of bytes of host memory used +host_seconds 1381.15 # Real time elapsed on the host +host_tick_rate 1715881736 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1832675505 # Number of instructions simulated -sim_seconds 2.371350 # Number of seconds simulated -sim_ticks 2371349716000 # Number of ticks simulated +sim_seconds 2.369896 # Number of seconds simulated +sim_ticks 2369896178000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55313.730657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.730657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 54567.414542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51567.414542 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 80822266000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 79731778000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 76438783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 75348295000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.434541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.434541 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276871387 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4159414000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 74276 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3936586000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74276 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 276872883 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55346.901240 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52346.901240 # average overall mshr miss latency -system.cpu.dcache.demand_hits 895774291 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 84981680000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.001711 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1535437 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 54452.292494 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency +system.cpu.dcache.demand_hits 895775787 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 83526604000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1533941 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 80375369000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001711 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1535437 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 78924781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1533941 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999748 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.966832 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4094.966269 # Average occupied blocks per context system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55346.901240 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52346.901240 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54452.292494 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 895774291 # number of overall hits -system.cpu.dcache.overall_miss_latency 84981680000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.001711 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1535437 # number of overall misses +system.cpu.dcache.overall_hits 895775787 # number of overall hits +system.cpu.dcache.overall_miss_latency 83526604000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1533941 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 80375369000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001711 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1535437 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 78924781000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1533941 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1529845 # number of replacements system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.966832 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.966269 # Cycle average of tags in use system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 993999000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74582 # number of writebacks +system.cpu.dcache.warmup_cycle 993944000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107259 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 1390241555 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18784.729586 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15784.729586 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1390221752 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 371994000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 312585000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1390241555 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18784.729586 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency system.cpu.icache.demand_hits 1390221752 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 371994000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 312585000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.679847 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1392.325794 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1392.325384 # Average occupied blocks per context system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18784.729586 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1390221752 # number of overall hits -system.cpu.icache.overall_miss_latency 371994000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses system.cpu.icache.overall_misses 19803 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 312585000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 18364 # number of replacements system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1392.325794 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1392.325384 # Cycle average of tags in use system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3784508000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.999986 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 72779 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 72779 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 41422 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 74856184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.972030 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1439542 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 57581680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972030 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1439542 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 1496 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 77792000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 1496 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 59840000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1496 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 74582 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 74582 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 67385 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 73506108000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.954499 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1413579 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56543160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954499 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1413579 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.032374 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.050081 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 41423 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 78640692000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.973340 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1512321 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 74072 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 76942944000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.952327 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1479672 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 60492840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.973340 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1512321 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 59186880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.952327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1479672 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.927467 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.046803 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 30391.242944 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1533.635543 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.881760 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.092816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28893.501877 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3041.393075 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 41423 # number of overall hits -system.cpu.l2cache.overall_miss_latency 78640692000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.973340 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1512321 # number of overall misses +system.cpu.l2cache.overall_hits 74072 # number of overall hits +system.cpu.l2cache.overall_miss_latency 76942944000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.952327 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1479672 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 60492840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.973340 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1512321 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 59186880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.952327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1479672 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1472894 # number of replacements -system.cpu.l2cache.sampled_refs 1505603 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1478797 # number of replacements +system.cpu.l2cache.sampled_refs 1511517 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31924.878487 # Cycle average of tags in use -system.cpu.l2cache.total_refs 48742 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31934.894953 # Cycle average of tags in use +system.cpu.l2cache.total_refs 75699 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66101 # number of writebacks +system.cpu.l2cache.writebacks 66099 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4742699432 # number of cpu cycles simulated +system.cpu.numCycles 4739792356 # number of cpu cycles simulated system.cpu.num_insts 1832675505 # Number of instructions executed system.cpu.num_refs 908401146 # Number of memory references system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls |