diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
| commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
| tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/long/40.perlbmk | |
| parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
| download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz | |
tests: update tests for TLB unification
Diffstat (limited to 'tests/long/40.perlbmk')
9 files changed, 104 insertions, 56 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 2eb72fecc..c9c4bd8a4 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.fuPool] @@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.l2cache] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 3ec2c9e61..2c39c411e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 6 2009 18:15:46 -M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip -M5 started Mar 6 2009 18:24:11 +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:41:37 M5 executing on maize -command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 655e48f3b..4f72e1349 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 233158 # Simulator instruction rate (inst/s) -host_mem_usage 213372 # Number of bytes of host memory used -host_seconds 7818.92 # Real time elapsed on the host -host_tick_rate 90186298 # Simulator tick rate (ticks/s) +host_inst_rate 236247 # Simulator instruction rate (inst/s) +host_mem_usage 213344 # Number of bytes of host memory used +host_seconds 7716.70 # Real time elapsed on the host +host_tick_rate 91380999 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.705159 # Number of seconds simulated @@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 561391036 # Nu system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 775959987 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 775335043 # DTB hits -system.cpu.dtb.misses 624944 # DTB misses +system.cpu.dtb.data_accesses 775959987 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 775335043 # DTB hits +system.cpu.dtb.data_misses 624944 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 516992085 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 516404963 # DTB read hits @@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 562621267 # Nu system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 348448092 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 348447899 # ITB hits -system.cpu.itb.misses 193 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 348448092 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 348447899 # ITB hits +system.cpu.itb.fetch_misses 193 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 4863763a5..d69895fd2 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -39,11 +39,11 @@ dcache_port=system.membus.port[2] icache_port=system.membus.port[1] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.tracer] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 3e0584ae3..c197c46fb 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:27:51 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:38:04 +M5 executing on maize +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index a2839e9d4..ebae3bb0f 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,17 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3467416 # Simulator instruction rate (inst/s) -host_mem_usage 202428 # Number of bytes of host memory used -host_seconds 579.39 # Real time elapsed on the host -host_tick_rate 1734081372 # Simulator tick rate (ticks/s) +host_inst_rate 5314394 # Simulator instruction rate (inst/s) +host_mem_usage 204196 # Number of bytes of host memory used +host_seconds 378.03 # Real time elapsed on the host +host_tick_rate 2657768720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated sim_ticks 1004710587000 # Number of ticks simulated -system.cpu.dtb.accesses 722298387 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 721864922 # DTB hits -system.cpu.dtb.misses 433465 # DTB misses +system.cpu.dtb.data_accesses 722298387 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 721864922 # DTB hits +system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 511488910 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 511070026 # DTB read hits @@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 210794896 # DTB write hits system.cpu.dtb.write_misses 14581 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2009421175 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2009421070 # ITB hits -system.cpu.itb.misses 105 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 2009421175 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 2009421070 # ITB hits +system.cpu.itb.fetch_misses 105 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2009421175 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index a7ffe8cab..8c5285f82 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.icache] @@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.l2cache] diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index bfb6dafd6..cdafa0ab2 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:29:29 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py long/40.perlbmk/alpha/tru64/simple-timing +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:45:29 +M5 executing on maize +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 87861b454..4c7aa8469 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2199489 # Simulator instruction rate (inst/s) -host_mem_usage 209876 # Number of bytes of host memory used -host_seconds 913.39 # Real time elapsed on the host -host_tick_rate 3081877276 # Simulator tick rate (ticks/s) +host_inst_rate 2595694 # Simulator instruction rate (inst/s) +host_mem_usage 211736 # Number of bytes of host memory used +host_seconds 773.97 # Real time elapsed on the host +host_tick_rate 3637030411 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated @@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4095.198740 # Cy system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks -system.cpu.dtb.accesses 722298387 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 721864922 # DTB hits -system.cpu.dtb.misses 433465 # DTB misses +system.cpu.dtb.data_accesses 722298387 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 721864922 # DTB hits +system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 511488910 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 511070026 # DTB read hits @@ -137,10 +141,22 @@ system.cpu.icache.total_refs 2009410475 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2009421176 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2009421071 # ITB hits -system.cpu.itb.misses 105 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 2009421176 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 2009421071 # ITB hits +system.cpu.itb.fetch_misses 105 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency |