Bus: Update the stats for the recent bus fix.

--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407

3 files changed, 52 insertions, 50 deletions

diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 155b89d4e..7985d0869 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -152,6 +152,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -181,6 +182,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.l2cache.mem_side
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
index b73b39051..6e1f5bd66 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 883544                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 162840                       # Number of bytes of host memory used
-host_seconds                                  2273.78                       # Real time elapsed on the host
-host_tick_rate                             1217345227                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1017888                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209744                       # Number of bytes of host memory used
+host_seconds                                  1973.68                       # Real time elapsed on the host
+host_tick_rate                             1403993769                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
-sim_seconds                                  2.767980                       # Number of seconds simulated
-sim_ticks                                2767979952000                       # Number of ticks simulated
+sim_seconds                                  2.771038                       # Number of seconds simulated
+sim_ticks                                2771037759000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24826.352085                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22826.352085                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 26811.881426                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23811.881426                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    36201588000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    39096871000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  33285204000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  34722295000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 26999.692460                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.692460                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits             210720109                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    1869675000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    2019226000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000355                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses               74787                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   1720101000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1794865000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000355                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses          74787                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 24834.823569                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 22834.823569                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 26821.043863                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23821.043863                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               720331943                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     38071263000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     41116097000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.002124                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses               1532979                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  35005305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  36517160000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.002124                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses          1532979                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 24834.823569                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 22834.823569                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 26821.043863                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23821.043863                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              720331943                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    38071263000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    41116097000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.002124                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses              1532979                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  35005305000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  36517160000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.002124                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses         1532979                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                1526048                       # number of replacements
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.361619                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.350762                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              795905000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              812770000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                    74589                       # number of writebacks
 system.cpu.dtb.accesses                     722298387                       # DTB accesses
 system.cpu.dtb.acv                                  0                       # DTB access violations
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                   210794896                       # DTB write hits
 system.cpu.dtb.write_misses                     14581                       # DTB write misses
 system.cpu.icache.ReadReq_accesses         2009421071                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15691.959230                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16916.289166                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13916.289166                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             2009410475                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      166272000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      179245000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    145080000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    147457000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          2009421071                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15691.959230                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 16916.289166                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13916.289166                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              2009410475                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       166272000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       179245000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    145080000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    147457000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15691.959230                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 16916.289166                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13916.289166                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             2009410475                       # number of overall hits
-system.cpu.icache.overall_miss_latency      166272000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      179245000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                10596                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    145080000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    147457000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                   9046                       # number of replacements
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1478.559454                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1478.550297                       # Cycle average of tags in use
 system.cpu.icache.total_refs               2009410475                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -160,28 +160,28 @@ system.cpu.itb.acv                                  0                       # IT
 system.cpu.itb.hits                        2009421071                       # ITB hits
 system.cpu.itb.misses                             105                       # ITB misses
 system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   1582944000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   1654896000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses             71952                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency    791472000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses        71952                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           1468788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                 29320                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   31668296000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency   33107764000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.980038                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses             1439468                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency  15834148000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.980038                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses        1439468                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses           2835                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 21821.516755                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22813.403880                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency     61864000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency     64676000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses             2835                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency     31185000                       # number of UpgradeReq MSHR miss cycles
@@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                  29320                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    33251240000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency    34762660000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.980970                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses              1511420                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                 29320                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   33251240000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency   34762660000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.980970                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses             1511420                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements               1473608                       # number of replacements
 system.cpu.l2cache.sampled_refs               1506166                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31924.676313                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             31923.721558                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   35763                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   66899                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       5535959904                       # number of cpu cycles simulated
+system.cpu.numCycles                       5542075518                       # number of cpu cycles simulated
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
 system.cpu.num_refs                         722823898                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
index aa60d7c13..fc28a8ff6 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
@@ -1,4 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
+0: system.remote_gdb.listener: listening for remote gdb on port 7007
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Increasing stack size by one page.
 warn: ignoring syscall sigprocmask(1, 0, ...)