diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/40.perlbmk | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/40.perlbmk')
17 files changed, 395 insertions, 392 deletions
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index d7298148c..f5ffa5534 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 4c38c001d..2316b9142 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:45:13 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 870c3ba76..c6cbb8474 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 161084 # Simulator instruction rate (inst/s) -host_mem_usage 215416 # Number of bytes of host memory used -host_seconds 11317.35 # Real time elapsed on the host -host_tick_rate 60889223 # Simulator tick rate (ticks/s) +host_inst_rate 299190 # Simulator instruction rate (inst/s) +host_mem_usage 211252 # Number of bytes of host memory used +host_seconds 6093.26 # Real time elapsed on the host +host_tick_rate 113092899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.689105 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 28355376 # Nu system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 71745000 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1283484985 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.565260 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1283484985 # Number of insts commited each cycle -system.cpu.commit.COM:count 2008987604 # Number of instructions committed -system.cpu.commit.COM:fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 39955347 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.COM:loads 511070026 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 721864922 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted +system.cpu.commit.branches 266706457 # Number of branches committed +system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle +system.cpu.commit.count 2008987604 # Number of instructions committed +system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. +system.cpu.commit.function_calls 39955347 # Number of function calls committed. +system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. +system.cpu.commit.loads 511070026 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 721864922 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 1530600 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999779 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4095.093805 # Cy system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107391 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 27367471 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 11874 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 29084935 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2889732822 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 703418574 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 551446436 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 94589845 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45736 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1252504 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle +system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running +system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 766409541 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 765750752 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 9774 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.787641 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 343688083 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 273848647 # Number of branches executed -system.cpu.iew.EXEC:nop 323098610 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.444031 # Inst execution rate -system.cpu.iew.EXEC:refs 766410290 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 251723816 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1598918223 # num instructions consuming a value -system.cpu.iew.WB:count 1989129822 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.699683 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1118735591 # num instructions producing a value -system.cpu.iew.WB:rate 1.443271 # insts written-back per cycle -system.cpu.iew.WB:sent 1990119861 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 273848647 # Number of branches executed +system.cpu.iew.exec_nop 323098610 # number of nop insts executed +system.cpu.iew.exec_rate 1.444031 # Inst execution rate +system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed +system.cpu.iew.exec_stores 251723816 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 84105156 # system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value +system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1118735591 # num instructions producing a value +system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle +system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2067604433 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 36218004 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1378074830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.500357 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1378074830 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.500211 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 522645709 # Nu system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle +system.cpu.iq.rate 1.500211 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 1480593 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881563 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.093197 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 1378209168 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 17364773 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 667601 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 717318588 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3251110860 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2789102688 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1858404761 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 538784806 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 94589845 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9995832 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 473435691 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 109436331 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 3141674529 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 20986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2820 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 26060288 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 67 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running +system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed +system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 3864626779 # The number of ROB reads system.cpu.rob.rob_writes 5411636382 # The number of ROB writes system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index b7ecd550d..01eff331e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:05:07 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 855c5964e..f1d866c8d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1477901 # Simulator instruction rate (inst/s) -host_mem_usage 224424 # Number of bytes of host memory used -host_seconds 1359.35 # Real time elapsed on the host -host_tick_rate 739109964 # Simulator tick rate (ticks/s) +host_inst_rate 5736498 # Simulator instruction rate (inst/s) +host_mem_usage 202144 # Number of bytes of host memory used +host_seconds 350.21 # Real time elapsed on the host +host_tick_rate 2868866718 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 9be1cb679..d0df4a5be 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 03731b56d..fd9623671 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:00:30 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c88cbd8f6..0966bdbb1 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 584935 # Simulator instruction rate (inst/s) -host_mem_usage 232204 # Number of bytes of host memory used -host_seconds 3434.55 # Real time elapsed on the host -host_tick_rate 819166202 # Simulator tick rate (ticks/s) +host_inst_rate 2647820 # Simulator instruction rate (inst/s) +host_mem_usage 209816 # Number of bytes of host memory used +host_seconds 758.73 # Real time elapsed on the host +host_tick_rate 3708113045 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.813468 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 1530144 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999806 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 10596 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 1479815 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.880371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.094050 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 1332688300 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_mem_refs 722298387 # number of memory refs system.cpu.num_store_insts 210809477 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 39 # Number of system calls +system.cpu.workload.num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 21ecdfc08..410b12d67 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 166a55741..ef09fb549 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:12:10 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:00:27 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 6525e4aa7..d75eda4b1 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 140843 # Simulator instruction rate (inst/s) -host_mem_usage 264636 # Number of bytes of host memory used -host_seconds 13386.13 # Real time elapsed on the host -host_tick_rate 64927108 # Simulator tick rate (ticks/s) +host_inst_rate 198311 # Simulator instruction rate (inst/s) +host_mem_usage 221048 # Number of bytes of host memory used +host_seconds 9507.00 # Real time elapsed on the host +host_tick_rate 91419245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885343131 # Number of instructions simulated sim_seconds 0.869123 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 38509304 # Nu system.cpu.BPredUnit.condPredicted 414146262 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 547821195 # Number of BP lookups system.cpu.BPredUnit.usedRAS 52353944 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 291352101 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 58391194 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1569639960 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.201138 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.832019 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 741490044 47.24% 47.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 428382990 27.29% 74.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 179836279 11.46% 85.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 75300710 4.80% 90.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 51350508 3.27% 94.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14363186 0.92% 94.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 16626388 1.06% 96.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 3898661 0.25% 96.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 58391194 3.72% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1569639960 # Number of insts commited each cycle -system.cpu.commit.COM:count 1885354147 # Number of instructions committed -system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 41577833 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1660589568 # Number of committed integer instructions. -system.cpu.commit.COM:loads 631390738 # Number of loads committed -system.cpu.commit.COM:membars 9986 # Number of memory barriers committed -system.cpu.commit.COM:refs 908389591 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 44034324 # The number of times a branch was mispredicted +system.cpu.commit.branches 291352101 # Number of branches committed +system.cpu.commit.bw_lim_events 58391194 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 1159545124 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1569639960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.201138 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 741490044 47.24% 47.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 428382990 27.29% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 179836279 11.46% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 75300710 4.80% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51350508 3.27% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14363186 0.92% 94.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16626388 1.06% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3898661 0.25% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58391194 3.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1569639960 # Number of insts commited each cycle +system.cpu.commit.count 1885354147 # Number of instructions committed +system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. +system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.int_insts 1660589568 # Number of committed integer instructions. +system.cpu.commit.loads 631390738 # Number of loads committed +system.cpu.commit.membars 9986 # Number of memory barriers committed +system.cpu.commit.refs 908389591 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 1885343131 # Number of Instructions Simulated system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated system.cpu.cpi 0.921978 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 1535477 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999735 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.913997 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999735 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 996679005 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34625.216763 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34030.134935 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4094.913997 # Cy system.cpu.dcache.total_refs 993970537 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 333433000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 106994 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 146923379 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 10558 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 87779592 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 3387651447 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 772293047 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 647864668 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 162682073 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 19702 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2558864 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 146923379 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 10558 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 87779592 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 3387651447 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 772293047 # Number of cycles decode is idle +system.cpu.decode.RunCycles 647864668 # Number of cycles decode is running +system.cpu.decode.SquashCycles 162682073 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 19702 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 2558864 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 24392 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.752702 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1541.532802 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.752702 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 367105078 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9381.938291 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6050.959331 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 367080251 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 5923199 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 358605233 # Number of branches executed -system.cpu.iew.EXEC:nop 1350849 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.388402 # Inst execution rate -system.cpu.iew.EXEC:refs 1176236253 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 407328146 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2464876715 # num instructions consuming a value -system.cpu.iew.WB:count 2378604713 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.531444 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1309943730 # num instructions producing a value -system.cpu.iew.WB:rate 1.368394 # insts written-back per cycle -system.cpu.iew.WB:sent 2386121679 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 46494560 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 358605233 # Number of branches executed +system.cpu.iew.exec_nop 1350849 # number of nop insts executed +system.cpu.iew.exec_rate 1.388402 # Inst execution rate +system.cpu.iew.exec_refs 1176236253 # number of memory reference insts executed +system.cpu.iew.exec_stores 407328146 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 11036637 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 946299703 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 229756 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 201953747 # system.cpu.iew.memOrderViolationEvents 2659902 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 7823566 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 38670994 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2464876715 # num instructions consuming a value +system.cpu.iew.wb_count 2378604713 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.531444 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1309943730 # num instructions producing a value +system.cpu.iew.wb_rate 1.368394 # insts written-back per cycle +system.cpu.iew.wb_sent 2386121679 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 5694776843 # number of integer regfile reads system.cpu.int_regfile_writes 1751148886 # number of integer regfile writes system.cpu.ipc 1.084624 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.084624 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1205851764 48.37% 48.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 11238449 0.45% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8633 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 48.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876474 0.28% 49.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501201 0.22% 49.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385525 0.94% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 797167964 31.97% 82.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 441731367 17.72% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2493136666 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 86890569 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.034852 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 482 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.03% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 55140629 63.46% 63.49% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 31725345 36.51% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1732322031 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.439188 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.577350 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 668978981 38.62% 38.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 360959007 20.84% 59.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 315091353 18.19% 77.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 182075740 10.51% 88.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 118045462 6.81% 94.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 56433729 3.26% 98.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 19322035 1.12% 99.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 5840762 0.34% 99.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5574962 0.32% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1732322031 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.434284 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1205851764 48.37% 48.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11238449 0.45% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 8633 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501201 0.22% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23385525 0.94% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 797167964 31.97% 82.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 441731367 17.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2493136666 # Type of FU issued system.cpu.iq.fp_alu_accesses 66051736 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 126602345 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 59166260 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 83365842 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 86890569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034852 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24113 0.03% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55140629 63.46% 63.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31725345 36.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 2513975499 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 6687198013 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 2319438453 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 1158104053 # Nu system.cpu.iq.iqSquashedInstsIssued 8314426 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 30366 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1709199023 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1732322031 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.439188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.577350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 668978981 38.62% 38.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 360959007 20.84% 59.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 315091353 18.19% 77.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 182075740 10.51% 88.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 118045462 6.81% 94.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56433729 3.26% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 19322035 1.12% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5840762 0.34% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5574962 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1732322031 # Number of insts issued each cycle +system.cpu.iq.rate 1.434284 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -469,10 +469,10 @@ system.cpu.l2cache.demand_mshr_misses 1480664 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.884291 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.091352 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28976.452018 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 2993.413242 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.884291 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.091352 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1559863 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34267.085819 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.382261 # average overall mshr miss latency @@ -503,28 +503,28 @@ system.cpu.misc_regfile_writes 13780014 # nu system.cpu.numCycles 1738245230 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 26815429 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1523726473 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 13358705 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 804669593 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 8858159876 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3258876297 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2595747724 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 616670755 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 162682073 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32941123 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1072021248 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 417025150 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 8441134726 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8500262 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 93807403 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 250407 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 26815429 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1523726473 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 13358705 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 804669593 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 8858159876 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 3258876297 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 2595747724 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 616670755 # Number of cycles rename is running +system.cpu.rename.SquashCycles 162682073 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 32941123 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 1072021248 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 417025150 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 8441134726 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 8500262 # count of serializing insts renamed +system.cpu.rename.skidInsts 93807403 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 250407 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 4556129692 # The number of ROB reads system.cpu.rob.rob_writes 6252480772 # The number of ROB writes system.cpu.timesIdled 1346475 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls +system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 4c80bccfd..97cb6c6e4 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout index 47a67193a..343cd2a25 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:14:25 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:03:45 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index a5bf8162c..fa8e0bd4e 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1065231 # Simulator instruction rate (inst/s) -host_mem_usage 252312 # Number of bytes of host memory used -host_seconds 1769.89 # Real time elapsed on the host -host_tick_rate 534279231 # Simulator tick rate (ticks/s) +host_inst_rate 3903299 # Simulator instruction rate (inst/s) +host_mem_usage 211416 # Number of bytes of host memory used +host_seconds 483.01 # Real time elapsed on the host +host_tick_rate 1957745790 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885336367 # Number of instructions simulated sim_seconds 0.945613 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 1404936302 # nu system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls +system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 53d197f66..f566d5f40 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout index 5f6cb9527..5a9581642 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:18:27 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:11:59 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 3345b6b66..064048304 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 561445 # Simulator instruction rate (inst/s) -host_mem_usage 260040 # Number of bytes of host memory used -host_seconds 3338.25 # Real time elapsed on the host -host_tick_rate 709922934 # Simulator tick rate (ticks/s) +host_inst_rate 2093812 # Simulator instruction rate (inst/s) +host_mem_usage 219156 # Number of bytes of host memory used +host_seconds 895.14 # Real time elapsed on the host +host_tick_rate 2647534553 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1874244950 # Number of instructions simulated sim_seconds 2.369902 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 1533653 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999746 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 19803 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 1479630 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881757 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.092817 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 1404936302 # nu system.cpu.num_load_insts 631387182 # Number of load instructions system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls +system.cpu.workload.num_syscalls 1411 # Number of system calls ---------- End Simulation Statistics ---------- |