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authorGabe Black <gblack@eecs.umich.edu>2007-03-11 19:06:46 -0400
committerGabe Black <gblack@eecs.umich.edu>2007-03-11 19:06:46 -0400
commitd9c3b636b0f85d5585d7a26ea8d64a2c5b4db024 (patch)
treed892a28f1fc02c2ac1187b3ca8647c84b213cd1f /tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
parent26f440c44e5e85dc3e03371d08a1e6587e5f50cf (diff)
downloadgem5-d9c3b636b0f85d5585d7a26ea8d64a2c5b4db024.tar.xz
vortex is a tru64 regression and not linux
--HG-- rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini => tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out => tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg => tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out => tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini => tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out => tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg => tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out => tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout extra : convert_revision : b62b8949628327d0a0ed2971772aa4f848764d54
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out')
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out405
1 files changed, 0 insertions, 405 deletions
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
deleted file mode 100644
index 52c225902..000000000
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
+++ /dev/null
@@ -1,405 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-