stats: Update stats for final tick and memory bandwidth patches

3 files changed, 24 insertions, 11 deletions

diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index e20a60e8c..1b963b10c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -205,7 +207,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
 
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index a3cf9c876..0aab67a06 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:45:59
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:56
+gem5 executing on zizzer
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index a84fb4906..32a07ce20 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.046914                       # Number of seconds simulated
 sim_ticks                                 46914279500                       # Number of ticks simulated
+final_tick                                46914279500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53929                       # Simulator instruction rate (inst/s)
-host_tick_rate                               28639497                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254456                       # Number of bytes of host memory used
-host_seconds                                  1638.10                       # Real time elapsed on the host
+host_inst_rate                                 107347                       # Simulator instruction rate (inst/s)
+host_tick_rate                               57007816                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216192                       # Number of bytes of host memory used
+host_seconds                                   822.94                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                    11164096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 599296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7712960                       # Number of bytes written to this memory
+system.physmem.num_reads                       174439                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120515                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      237967973                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  12774277                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     164405381                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     402373354                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv