tests: update tests for TLB unification

1 files changed, 28 insertions, 12 deletions

diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index c3cb349a5..9dcaad468 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 261905                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216920                       # Number of bytes of host memory used
-host_seconds                                   303.90                       # Real time elapsed on the host
-host_tick_rate                               89289765                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 259851                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 216888                       # Number of bytes of host memory used
+host_seconds                                   306.30                       # Real time elapsed on the host
+host_tick_rate                               88589448                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.027135                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles           19520694                       # Nu
 system.cpu.decode.DECODE:SquashCycles         1290101                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts         284696                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles         144719                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                      36599689                       # DTB accesses
-system.cpu.dtb.acv                                 39                       # DTB access violations
-system.cpu.dtb.hits                          36425481                       # DTB hits
-system.cpu.dtb.misses                          174208                       # DTB misses
+system.cpu.dtb.data_accesses                 36599689                       # DTB accesses
+system.cpu.dtb.data_acv                            39                       # DTB access violations
+system.cpu.dtb.data_hits                     36425481                       # DTB hits
+system.cpu.dtb.data_misses                     174208                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 21541288                       # DTB read accesses
 system.cpu.dtb.read_acv                            37                       # DTB read access violations
 system.cpu.dtb.read_hits                     21383020                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined         9777311                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             49841                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved            421                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined      6793875                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                      13412237                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          13386072                       # ITB hits
-system.cpu.itb.misses                           26165                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                13412237                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    13386072                       # ITB hits
+system.cpu.itb.fetch_misses                     26165                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          143494                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754                       # average ReadExReq mshr miss latency