diff options
| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
| commit | ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch) | |
| tree | 93b9bd8be890468c550b85eae4b467285b4d6811 /tests/long/50.vortex/ref/alpha/tru64/o3-timing | |
| parent | 7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff) | |
| download | gem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz | |
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/tru64/o3-timing')
3 files changed, 20 insertions, 12 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 33c06f76d..821bc3ec9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 84d8d4369..dddba13b1 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:55:23 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:28:19 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 254fb17d5..d2ad10f5b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254468 # Simulator instruction rate (inst/s) -host_mem_usage 199708 # Number of bytes of host memory used -host_seconds 312.78 # Real time elapsed on the host -host_tick_rate 86754409 # Simulator tick rate (ticks/s) +host_inst_rate 172212 # Simulator instruction rate (inst/s) +host_mem_usage 201796 # Number of bytes of host memory used +host_seconds 462.17 # Real time elapsed on the host +host_tick_rate 58711424 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated @@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 211325 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.995440 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.324152 # Average occupied blocks per context system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency @@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses 85936 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.936032 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1916.994169 # Average occupied blocks per context system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency @@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses 188071 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.089962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.474123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2947.876007 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15536.049051 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency |