Merge with the main repo.

--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh

1 files changed, 15 insertions, 4 deletions

diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 02c53f6a1..59b869a9f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.134277                       # Number of seconds simulated
 sim_ticks                                134276988000                       # Number of ticks simulated
+final_tick                               134276988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1277823                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1942278600                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 201212                       # Number of bytes of host memory used
-host_seconds                                    69.13                       # Real time elapsed on the host
+host_inst_rate                                1801981                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2738992827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215584                       # Number of bytes of host memory used
+host_seconds                                    49.02                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                    11121920                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 558272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7712384                       # Number of bytes written to this memory
+system.physmem.num_reads                       173780                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120506                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       82828191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4157615                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      57436379                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     140264570                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv