diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/50.vortex/ref/alpha/tru64 | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/50.vortex/ref/alpha/tru64')
9 files changed, 581 insertions, 614 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index b77e3983a..5fb4a0cfa 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index aa460e79e..c3421945c 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:06 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 16:19:32 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 104900991500 because target called exit() +Exiting @ tick 104166942500 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 0547798c7..81763d717 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 31368 # Simulator instruction rate (inst/s) -host_mem_usage 223704 # Number of bytes of host memory used -host_seconds 2816.26 # Real time elapsed on the host -host_tick_rate 37248320 # Simulator tick rate (ticks/s) +host_inst_rate 58405 # Simulator instruction rate (inst/s) +host_mem_usage 209896 # Number of bytes of host memory used +host_seconds 1512.56 # Real time elapsed on the host +host_tick_rate 68868083 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.104901 # Number of seconds simulated -sim_ticks 104900991500 # Number of ticks simulated +sim_seconds 0.104167 # Number of seconds simulated +sim_ticks 104166942500 # Number of ticks simulated system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 434959 system.cpu.Execution-Unit.predictedTakenIncorrect 217237 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 156429013 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 103882132 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 156429280 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 103882399 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2136233 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 84.755939 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 2135966 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 85.354290 # Percentage of cycles cpu is active system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed system.cpu.comInts 30457224 # Number of Integer instructions committed @@ -42,28 +42,28 @@ system.cpu.comStores 14844619 # Nu system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.374919 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.374919 # CPI: Total CPI of All Threads +system.cpu.cpi 2.358301 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.358301 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 38051.171708 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34943.916006 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 37505.438897 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34394.916565 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2312217500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2279055500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2123402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2090041500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56416.363760 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53416.289024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8303642500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7862076500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 52898.208639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49865.139506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7595019000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7159537000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. @@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 51049.814620 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10615860000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses -system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 48320.843773 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 45264.742297 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9874074500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9985478500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 9249578500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995330 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.871208 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.995297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4076.738170 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 51049.814620 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 48320.843773 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 45264.742297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34682064 # number of overall hits -system.cpu.dcache.overall_miss_latency 10615860000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses -system.cpu.dcache.overall_misses 207951 # number of overall misses +system.cpu.dcache.overall_hits 34685671 # number of overall hits +system.cpu.dcache.overall_miss_latency 9874074500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 204344 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9985478500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 9249578500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.871208 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.738170 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 834930000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 149164 # number of writebacks +system.cpu.dcache.warmup_cycle 834588000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 161221 # number of writebacks system.cpu.dtb.data_accesses 34987415 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 34890015 # DTB hits @@ -126,50 +126,50 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 97023272 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 19062.290643 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15844.379626 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 96943862 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1513736500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_avg_miss_latency 19054.387931 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15836.123818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 96943861 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1513128000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 79410 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1586 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1233073000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 79411 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1587 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1232430500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000802 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 77824 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 800 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1245.680793 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1245.680780 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 97023272 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 19062.290643 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency -system.cpu.icache.demand_hits 96943862 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1513736500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_avg_miss_latency 19054.387931 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15836.123818 # average overall mshr miss latency +system.cpu.icache.demand_hits 96943861 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1513128000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000818 # miss rate for demand accesses -system.cpu.icache.demand_misses 79410 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1586 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1233073000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 79411 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1587 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1232430500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000802 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 77824 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.914717 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1873.340733 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.914428 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1872.748134 # Average occupied blocks per context system.cpu.icache.overall_accesses 97023272 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 19062.290643 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 19054.387931 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15836.123818 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 96943862 # number of overall hits -system.cpu.icache.overall_miss_latency 1513736500 # number of overall miss cycles +system.cpu.icache.overall_hits 96943861 # number of overall hits +system.cpu.icache.overall_miss_latency 1513128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000818 # miss rate for overall accesses -system.cpu.icache.overall_misses 79410 # number of overall misses -system.cpu.icache.overall_mshr_hits 1586 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1233073000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 79411 # number of overall misses +system.cpu.icache.overall_mshr_hits 1587 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1232430500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000802 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 77824 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 75778 # number of replacements system.cpu.icache.sampled_refs 77824 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1873.340733 # Cycle average of tags in use -system.cpu.icache.total_refs 96943862 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1872.748134 # Cycle average of tags in use +system.cpu.icache.total_refs 96943861 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 31982342 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.421067 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.421067 # IPC: Total IPC of All Threads +system.cpu.idleCycles 30511976 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.424034 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.424034 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,105 +201,96 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.707450 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226443 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 7525926000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740992500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_avg_miss_latency 52440.979168 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.144510 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 6894887500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259179000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 138590 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52302.271309 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.863791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 95311 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2263590000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.312281 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1731370500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312281 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43279 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51817.854172 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.356529 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 186907000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144288500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits +system.cpu.l2cache.ReadReq_avg_miss_latency 52303.399887 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.932662 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 96118 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2221430000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.306458 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 42472 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1699089500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.306458 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 42472 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 161221 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 161221 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.646134 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.718111 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 282168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52405.560939 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 95365 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9789516000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.662028 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186803 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 52407.387713 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.313588 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 108217 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9116317500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.616480 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 173951 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7472363000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.662028 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 6958268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.616480 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 173951 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.089575 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.471967 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2935.193659 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15465.399858 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.086814 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.481065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2844.720641 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15763.536508 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 282168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52405.560939 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52407.387713 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.313588 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 95365 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9789516000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.662028 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186803 # number of overall misses +system.cpu.l2cache.overall_hits 108217 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9116317500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.616480 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 173951 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7472363000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.662028 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 6958268500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.616480 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 173951 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 147725 # number of replacements -system.cpu.l2cache.sampled_refs 173054 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147575 # number of replacements +system.cpu.l2cache.sampled_refs 172919 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18400.593517 # Cycle average of tags in use -system.cpu.l2cache.total_refs 111816 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18608.257148 # Cycle average of tags in use +system.cpu.l2cache.total_refs 124175 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120606 # number of writebacks -system.cpu.numCycles 209801984 # number of cpu cycles simulated -system.cpu.runCycles 177819642 # Number of cycles cpu stages are processed. +system.cpu.l2cache.writebacks 120508 # number of writebacks +system.cpu.numCycles 208333886 # number of cpu cycles simulated +system.cpu.runCycles 177821910 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 112774700 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 111306602 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 97027284 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 46.247076 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 121437923 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 88364061 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 42.117839 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 119986198 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 46.572973 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 119969888 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 88363998 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 42.414607 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 118518100 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 42.809789 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 174570714 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 43.111463 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 173102616 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 16.792630 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 121461311 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 16.910965 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 119993213 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 42.106691 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 209801984 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 42.403411 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 208333886 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 0c3775172..4fc48d6be 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 90ad95ec6..5eaa6d66d 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:53:46 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:41:46 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 27109454000 because target called exit() +Exiting @ tick 27033689000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index aa0ed940f..e70c0ce38 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 111480 # Simulator instruction rate (inst/s) -host_mem_usage 216720 # Number of bytes of host memory used -host_seconds 713.95 # Real time elapsed on the host -host_tick_rate 37970836 # Simulator tick rate (ticks/s) +host_inst_rate 221900 # Simulator instruction rate (inst/s) +host_mem_usage 202972 # Number of bytes of host memory used +host_seconds 358.68 # Real time elapsed on the host +host_tick_rate 75369122 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.027109 # Number of seconds simulated -sim_ticks 27109454000 # Number of ticks simulated +sim_seconds 0.027034 # Number of seconds simulated +sim_ticks 27033689000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 8023938 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14145639 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 34256 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 455419 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 10571328 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 16274912 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1940184 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 8073345 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14152511 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 36189 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 458905 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10574319 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 16281513 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1942543 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3318027 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3315405 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 51708884 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.708423 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.329205 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 51596234 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.712153 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.330354 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 22519798 43.55% 43.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 11308699 21.87% 65.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 5100268 9.86% 75.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3555628 6.88% 82.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2564108 4.96% 87.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1506181 2.91% 90.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 1020225 1.97% 92.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 815950 1.58% 93.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3318027 6.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 22410479 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 11292136 21.89% 65.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5122096 9.93% 75.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3547417 6.88% 82.12% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2566622 4.97% 87.10% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1508057 2.92% 90.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1006074 1.95% 91.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 827948 1.60% 93.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3315405 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 51708884 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 51596234 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360224 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 362306 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8384811 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8339248 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.681213 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.681213 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20456575 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20307098 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4527091000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007307 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149477 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 87887 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1284503500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61590 # number of ReadReq MSHR misses +system.cpu.cpi 0.679309 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.679309 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20462752 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30131.608065 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20434.335315 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20316340 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4411629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007155 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 146412 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 84834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1258305500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61578 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13566176 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 33748584999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071660 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1047201 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900041 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 5258205499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010070 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 147160 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 31003.810080 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32919.803194 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13581378 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 31995900999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.070620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1031999 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 888502 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 4723892999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009820 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143497 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.209324 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.294463 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35069952 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31984.941646 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33873274 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38275675999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.034123 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1196678 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 987928 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6542708999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005952 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 208750 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 35076129 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30895.443100 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33897718 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 36407529999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.033596 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1178411 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 973336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5982198499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005847 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 205075 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995492 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4077.536069 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 35069952 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31984.941646 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.995480 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.485052 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 35076129 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30895.443100 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33873274 # number of overall hits -system.cpu.dcache.overall_miss_latency 38275675999 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.034123 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1196678 # number of overall misses -system.cpu.dcache.overall_mshr_hits 987928 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6542708999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005952 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 208750 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33897718 # number of overall hits +system.cpu.dcache.overall_miss_latency 36407529999 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.033596 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1178411 # number of overall misses +system.cpu.dcache.overall_mshr_hits 973336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5982198499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005847 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 205075 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 200988 # number of replacements -system.cpu.dcache.sampled_refs 205084 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200979 # number of replacements +system.cpu.dcache.sampled_refs 205075 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.536069 # Cycle average of tags in use -system.cpu.dcache.total_refs 33881789 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 181403000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 149251 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3489554 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 96109 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3659886 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101890177 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28536030 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19538571 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1305079 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 281240 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144729 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 36643462 # DTB accesses -system.cpu.dtb.data_acv 34 # DTB access violations -system.cpu.dtb.data_hits 36467174 # DTB hits -system.cpu.dtb.data_misses 176288 # DTB misses +system.cpu.dcache.tagsinuse 4077.485052 # Cycle average of tags in use +system.cpu.dcache.total_refs 33897762 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 181365000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 161485 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3372983 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97431 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3660168 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101877731 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28530714 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19554245 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1300005 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 281200 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 138292 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 36642762 # DTB accesses +system.cpu.dtb.data_acv 38 # DTB access violations +system.cpu.dtb.data_hits 36466941 # DTB hits +system.cpu.dtb.data_misses 175821 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 21569273 # DTB read accesses -system.cpu.dtb.read_acv 32 # DTB read access violations -system.cpu.dtb.read_hits 21411172 # DTB read hits -system.cpu.dtb.read_misses 158101 # DTB read misses -system.cpu.dtb.write_accesses 15074189 # DTB write accesses +system.cpu.dtb.read_accesses 21568925 # DTB read accesses +system.cpu.dtb.read_acv 36 # DTB read access violations +system.cpu.dtb.read_hits 21411469 # DTB read hits +system.cpu.dtb.read_misses 157456 # DTB read misses +system.cpu.dtb.write_accesses 15073837 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15056002 # DTB write hits -system.cpu.dtb.write_misses 18187 # DTB write misses -system.cpu.fetch.Branches 16274912 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13386326 # Number of cache lines fetched -system.cpu.fetch.Cycles 33268098 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 152194 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103463438 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 573170 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.300170 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13386326 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9964122 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.908254 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 53013963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.951626 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.945013 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 15055472 # DTB write hits +system.cpu.dtb.write_misses 18365 # DTB write misses +system.cpu.fetch.Branches 16281513 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13394440 # Number of cache lines fetched +system.cpu.fetch.Cycles 33285984 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 153835 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103456008 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 576870 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.301134 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13394440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 10015888 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.913464 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 52896239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.955829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.944816 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 33159204 62.55% 62.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1896528 3.58% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1503537 2.84% 68.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1853022 3.50% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3942692 7.44% 79.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1853723 3.50% 83.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 688430 1.30% 84.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1103809 2.08% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7013018 13.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33031612 62.45% 62.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1863332 3.52% 65.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1548849 2.93% 68.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1858475 3.51% 72.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3937136 7.44% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1852242 3.50% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 690247 1.30% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1146451 2.17% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6967895 13.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53013963 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 13386326 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9552.485505 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6054.988859 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297330 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 850133000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006648 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88996 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2824 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 521770500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006437 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 86172 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 52896239 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 13394440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9549.980865 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6051.228388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13305596 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 848458500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006633 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88844 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2837 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 520448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 86007 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.313284 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.705439 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13386326 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9552.485505 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297330 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 850133000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006648 # miss rate for demand accesses -system.cpu.icache.demand_misses 88996 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2824 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 521770500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006437 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 86172 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13394440 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9549.980865 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency +system.cpu.icache.demand_hits 13305596 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 848458500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006633 # miss rate for demand accesses +system.cpu.icache.demand_misses 88844 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2837 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 520448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006421 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 86007 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.936859 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1918.688120 # Average occupied blocks per context -system.cpu.icache.overall_accesses 13386326 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9552.485505 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.936980 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1918.935161 # Average occupied blocks per context +system.cpu.icache.overall_accesses 13394440 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9549.980865 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297330 # number of overall hits -system.cpu.icache.overall_miss_latency 850133000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006648 # miss rate for overall accesses -system.cpu.icache.overall_misses 88996 # number of overall misses -system.cpu.icache.overall_mshr_hits 2824 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 521770500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006437 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 86172 # number of overall MSHR misses +system.cpu.icache.overall_hits 13305596 # number of overall hits +system.cpu.icache.overall_miss_latency 848458500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006633 # miss rate for overall accesses +system.cpu.icache.overall_misses 88844 # number of overall misses +system.cpu.icache.overall_mshr_hits 2837 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 520448000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006421 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 86007 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 84124 # number of replacements -system.cpu.icache.sampled_refs 86171 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83959 # number of replacements +system.cpu.icache.sampled_refs 86006 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1918.688120 # Cycle average of tags in use -system.cpu.icache.total_refs 13297330 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1918.935161 # Cycle average of tags in use +system.cpu.icache.total_refs 13305596 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1204946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14764091 # Number of branches executed -system.cpu.iew.EXEC:nop 9400465 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.566510 # Inst execution rate -system.cpu.iew.EXEC:refs 36986360 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15307304 # Number of stores executed +system.cpu.idleCycles 1171140 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14765953 # Number of branches executed +system.cpu.iew.EXEC:nop 9399098 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.570651 # Inst execution rate +system.cpu.iew.EXEC:refs 36985556 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15306955 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42224308 # num instructions consuming a value -system.cpu.iew.WB:count 84456261 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765793 # average fanout of values written-back +system.cpu.iew.WB:consumers 42195611 # num instructions consuming a value +system.cpu.iew.WB:count 84441959 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765718 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32335073 # num instructions producing a value -system.cpu.iew.WB:rate 1.557690 # insts written-back per cycle -system.cpu.iew.WB:sent 84693859 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 401805 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 605778 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23014883 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5009 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 349401 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16347988 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 99082046 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21679056 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539226 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84934458 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 11054 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32309953 # num instructions producing a value +system.cpu.iew.WB:rate 1.561791 # insts written-back per cycle +system.cpu.iew.WB:sent 84679067 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 403539 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 558736 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23014663 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5005 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 344896 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16344120 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 99062445 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21678601 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 539249 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84921008 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9867 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8978 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1305079 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 8786 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1300005 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 41358 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 953186 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 947297 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 703 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 20710 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1355 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2635484 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1503369 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 20710 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 131758 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 270047 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.467970 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.467970 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 20504 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1356 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2635264 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1499501 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 20504 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 133144 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 270395 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.472085 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.472085 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47968991 56.12% 56.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 42906 0.05% 56.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 47958643 56.12% 56.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 42972 0.05% 56.17% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122147 0.14% 56.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122098 0.14% 56.31% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122353 0.14% 56.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38520 0.05% 56.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122222 0.14% 56.45% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.45% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38519 0.05% 56.50% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21790369 25.49% 82.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388261 18.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 21787306 25.49% 81.99% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388360 18.01% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 85473684 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 995540 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011647 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 85460257 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 970619 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011358 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 102737 10.32% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 453943 45.60% 55.92% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 438860 44.08% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 98326 10.13% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 436344 44.96% 55.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 435949 44.91% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 53013963 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.612286 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.719350 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 52896239 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.615621 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720411 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 17564950 33.13% 33.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14012876 26.43% 59.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 8103290 15.29% 74.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4796735 9.05% 83.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4597424 8.67% 92.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2085134 3.93% 96.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1155738 2.18% 98.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 468299 0.88% 99.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 229517 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 17480622 33.05% 33.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 13990970 26.45% 59.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 8059116 15.24% 74.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 4840128 9.15% 83.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 4581404 8.66% 92.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2086569 3.94% 96.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1156021 2.19% 98.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 475188 0.90% 99.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 226221 0.43% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 53013963 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.576455 # Inst issue rate -system.cpu.iq.iqInstsAdded 89676572 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85473684 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 5009 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9869392 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 46778 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6797277 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 52896239 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.580625 # Inst issue rate +system.cpu.iq.iqInstsAdded 89658342 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85460257 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9847468 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 48230 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 422 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6786581 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 13413339 # ITB accesses +system.cpu.itb.fetch_accesses 13421357 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 13386326 # ITB hits -system.cpu.itb.fetch_misses 27013 # ITB misses +system.cpu.itb.fetch_hits 13394440 # ITB hits +system.cpu.itb.fetch_misses 26917 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,107 +343,98 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 61 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 4924813000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.999575 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143434 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4479705500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999575 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143434 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 103271 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1518815500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.301094 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44490 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1380712500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.301094 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44490 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3671 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 124700500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3671 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113902500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3671 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 149251 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 149251 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 143498 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34310.090850 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31208.995937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 12072 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 4509238000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.915873 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 131426 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4101673500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915873 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 131426 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34134.410943 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.923979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 103938 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1489830500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.295737 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43646 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1354463000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43646 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 161485 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 161485 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.688286 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.759972 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 291256 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34288.480982 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 103332 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6443628500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645219 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 187924 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 291082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34266.293296 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 116010 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 5999068500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.601453 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 175072 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5860418000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645219 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 187924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 5456136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.601453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 175072 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.096999 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.471977 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3178.468873 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15465.728229 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 291256 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34288.480982 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.094631 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.481096 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3100.873906 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15764.562961 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 291082 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34266.293296 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 103332 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6443628500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645219 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 187924 # number of overall misses +system.cpu.l2cache.overall_hits 116010 # number of overall hits +system.cpu.l2cache.overall_miss_latency 5999068500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.601453 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 175072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5860418000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645219 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 187924 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 5456136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.601453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 175072 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 148884 # number of replacements -system.cpu.l2cache.sampled_refs 174227 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148714 # number of replacements +system.cpu.l2cache.sampled_refs 174071 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18644.197102 # Cycle average of tags in use -system.cpu.l2cache.total_refs 119918 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18865.436867 # Cycle average of tags in use +system.cpu.l2cache.total_refs 132289 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120621 # number of writebacks -system.cpu.memDep0.conflictingLoads 12607383 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11255649 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 23014883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16347988 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 54218909 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2001211 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120514 # number of writebacks +system.cpu.memDep0.conflictingLoads 12522416 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11202183 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 23014663 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16344120 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 54067379 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1899423 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 58273 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28932787 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1273359 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121782078 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 101070010 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60804975 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19289152 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1305079 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1405067 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8258094 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 80667 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5283 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2766751 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5281 # count of temporary serializing insts renamed -system.cpu.timesIdled 41950 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 50756 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28921656 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1270692 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121761220 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 101056260 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60792051 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19304913 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1300005 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1392613 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8245170 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 77629 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5282 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2690297 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5280 # count of temporary serializing insts renamed +system.cpu.timesIdled 40629 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 1aa6cf383..6c6429621 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index a83443919..6bbe0f2d0 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:57:42 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:47:45 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 135015129000 because target called exit() +Exiting @ tick 134276988000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index e11ad72a2..ba780f9a8 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159310 # Simulator instruction rate (inst/s) -host_mem_usage 215356 # Number of bytes of host memory used -host_seconds 76.20 # Real time elapsed on the host -host_tick_rate 1771821789 # Simulator tick rate (ticks/s) +host_inst_rate 1350777 # Simulator instruction rate (inst/s) +host_mem_usage 201544 # Number of bytes of host memory used +host_seconds 65.40 # Real time elapsed on the host +host_tick_rate 2053162286 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.135015 # Number of seconds simulated -sim_ticks 135015129000 # Number of ticks simulated +sim_seconds 0.134277 # Number of seconds simulated +sim_ticks 134276988000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37754.336306 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34754.336306 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2294180000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2111882000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55984.400584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52984.400584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8240064000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7798509000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 50657.337546 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10534244000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses -system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9910391000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995838 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4078.950714 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 50657.337546 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34682064 # number of overall hits -system.cpu.dcache.overall_miss_latency 10534244000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses -system.cpu.dcache.overall_misses 207951 # number of overall misses +system.cpu.dcache.overall_hits 34685671 # number of overall hits +system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 204344 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9910391000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.950714 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 943578000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 149164 # number of writebacks +system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 161222 # number of writebacks system.cpu.dtb.data_accesses 34987415 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 34890015 # DTB hits @@ -90,13 +90,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18802.449108 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15802.449108 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1437184000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1207876000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -108,31 +108,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18802.449108 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1437184000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1207876000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.913991 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1871.853872 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.913772 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18802.449108 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1437184000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1207876000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1871.853872 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,37 +164,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 7463248000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 94094 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2241616000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.314194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43108 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1724320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43108 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51596.340449 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 186108000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144280000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.639727 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 94148 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9704864000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.664691 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 186632 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7465280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.664691 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 186632 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.088307 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.473299 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2893.659899 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15509.045444 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.085649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.482430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 94148 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9704864000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.664691 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 186632 # number of overall misses +system.cpu.l2cache.overall_hits 107000 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 173780 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7465280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.664691 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 186632 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 147555 # number of replacements -system.cpu.l2cache.sampled_refs 172883 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147405 # number of replacements +system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18402.705343 # Cycle average of tags in use -system.cpu.l2cache.total_refs 110598 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use +system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120604 # number of writebacks +system.cpu.l2cache.writebacks 120506 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270030258 # number of cpu cycles simulated +system.cpu.numCycles 268553976 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls |