inorder: update regressions from RAS fix

2 files changed, 154 insertions, 154 deletions

diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 52617316d..14eb56bed 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jun 24 2010 14:21:27
-M5 revision ec51e8700a87 7479 default qtip tip update_regr
-M5 started Jun 24 2010 14:21:29
+M5 compiled Jun 25 2010 15:39:41
+M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
+M5 started Jun 25 2010 16:11:25
 M5 executing on zooks
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index fd3c85c9d..aeef950c2 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,37 +1,37 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  51998                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 168584                       # Number of bytes of host memory used
-host_seconds                                  1698.93                       # Real time elapsed on the host
-host_tick_rate                               62320733                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  46297                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 167032                       # Number of bytes of host memory used
+host_seconds                                  1908.12                       # Real time elapsed on the host
+host_tick_rate                               55055354                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
-sim_seconds                                  0.105878                       # Number of seconds simulated
-sim_ticks                                105878306500                       # Number of ticks simulated
+sim_seconds                                  0.105052                       # Number of seconds simulated
+sim_ticks                                105052358500                       # Number of ticks simulated
 system.cpu.AGEN-Unit.agens                   35224018                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       40.484338                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits           4662108                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups       11515831                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect      1659774                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect      2359487                       # Number of conditional branches incorrect
+system.cpu.Branch-Predictor.BTBHitPct       41.015608                       # BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHits           4719981                       # Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups       11507768                       # Number of BTB lookups
+system.cpu.Branch-Predictor.RASInCorrect         1778                       # Number of incorrect RAS predictions.
+system.cpu.Branch-Predictor.condIncorrect       652196                       # Number of conditional branches incorrect
 system.cpu.Branch-Predictor.condPredicted      8920848                       # Number of conditional branches predicted
 system.cpu.Branch-Predictor.lookups          13754477                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken      5781163                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken      7973314                       # Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.predictedNotTaken      5723290                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken      8031187                       # Number of Branches Predicted As Taken (True).
 system.cpu.Branch-Predictor.usedRAS           1659774                       # Number of times the RAS was used to get a target.
 system.cpu.Execution-Unit.executions         53075554                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct     17.154320                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted        2359487                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted          11394990                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect       485820                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect      1873667                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Execution-Unit.mispredictPct      4.741700                       # Percentage of Incorrect Branches Predicts
+system.cpu.Execution-Unit.mispredicted         652196                       # Number of Branches Incorrectly Predicted
+system.cpu.Execution-Unit.predicted          13102281                       # Number of Branches Incorrectly Predicted
+system.cpu.Execution-Unit.predictedNotTakenIncorrect       434959                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect       217237                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.Mult-Div-Unit.multiplies             41101                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses    156428919                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads     103882038                       # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses    156428920                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads     103882039                       # Number of Reads from Register File
 system.cpu.RegFile-Manager.regFileWrites     52546881                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards        2136327                       # Number of Registers Read Through Forwarding Logic
-system.cpu.activity                         85.568977                       # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards        2136326                       # Number of Registers Read Through Forwarding Logic
+system.cpu.activity                         84.633296                       # Percentage of cycles cpu is active
 system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
 system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
 system.cpu.comInts                           30457224                       # Number of Integer instructions committed
@@ -42,26 +42,26 @@ system.cpu.comStores                         14844619                       # Nu
 system.cpu.committedInsts                    88340673                       # Number of Instructions Simulated (Per-Thread)
 system.cpu.committedInsts_total              88340673                       # Number of Instructions Simulated (Total)
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.cpi                               2.397046                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total                         2.397046                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.378346                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total                         2.378346                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38170.794523                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35065.488925                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38171.526841                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35064.773064                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               20215872                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2319486500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     2319531000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002997                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                60766                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2130789500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2130746000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56329.688303                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53329.688303                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56426.999259                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53426.999259                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              14463584                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    8437793000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    8452369500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.010250                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              149793                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   7988414000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   8002990500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.010250                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         149793                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -73,31 +73,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51089.146035                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48058.755503                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 51158.585005                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48127.776538                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                34679456                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     10757279500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     10771900500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.006035                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                210559                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  10119203500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10133736500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.006035                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           210559                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995318                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4076.822350                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.995308                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4076.781631                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51089.146035                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48058.755503                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 51158.585005                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48127.776538                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               34679456                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    10757279500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    10771900500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.006035                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               210559                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  10119203500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10133736500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.006035                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          210559                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -105,9 +105,9 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                 200248                       # number of replacements
 system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4076.822350                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4076.781631                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              841843000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              838762000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   147714                       # number of writebacks
 system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
@@ -125,72 +125,72 @@ system.cpu.dtb.write_accesses                14620629                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                    14613377                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
-system.cpu.icache.ReadReq_accesses           98672431                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 19067.834064                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15854.703492                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               98591653                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     1540261500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000819                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                80778                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              3006                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency   1233052000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000788                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           77772                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses           97023272                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 19069.814885                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15852.089330                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               96943862                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency     1514334000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000818                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                79410                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits              1586                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency   1233673000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000802                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           77824                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          800                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                1267.701139                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                1245.680793                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets         4000                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            98672431                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 19067.834064                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15854.703492                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                98591653                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      1540261500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000819                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 80778                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               3006                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   1233052000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000788                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            77772                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            97023272                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 19069.814885                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15852.089330                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                96943862                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency      1514334000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000818                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 79410                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits               1586                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency   1233673000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000802                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            77824                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.914796                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1873.502207                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           98672431                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 19067.834064                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15854.703492                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.914669                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1873.241202                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           97023272                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 19069.814885                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15852.089330                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               98591653                       # number of overall hits
-system.cpu.icache.overall_miss_latency     1540261500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000819                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                80778                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              3006                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   1233052000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000788                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           77772                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               96943862                       # number of overall hits
+system.cpu.icache.overall_miss_latency     1514334000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000818                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                79410                       # number of overall misses
+system.cpu.icache.overall_mshr_hits              1586                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency   1233673000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000802                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           77824                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  75726                       # number of replacements
-system.cpu.icache.sampled_refs                  77772                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                  75778                       # number of replacements
+system.cpu.icache.sampled_refs                  77824                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1873.502207                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 98591653                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1873.241202                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 96943862                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                        30558645                       # Number of cycles cpu's stages were not processed
-system.cpu.ipc                               0.417180                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total                         0.417180                       # IPC: Total IPC of All Threads
+system.cpu.idleCycles                        32286171                       # Number of cycles cpu's stages were not processed
+system.cpu.ipc                               0.420460                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total                         0.420460                       # IPC: Total IPC of All Threads
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                98676443                       # ITB accesses
+system.cpu.itb.fetch_accesses                97027284                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    98672432                       # ITB hits
+system.cpu.itb.fetch_hits                    97023273                       # ITB hits
 system.cpu.itb.fetch_misses                      4011                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -201,104 +201,104 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52334.072769                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226358                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   7514021500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.396941                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.233323                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency   7528713000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses            143578                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   5743152500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   5743153500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       143578                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            138538                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52300.064414                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.819527                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 95069                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    2273431500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.313770                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               43469                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1738969500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313770                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          43469                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            138590                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52301.497653                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.842643                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 95122                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    2273441500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.313645                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               43468                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1738930500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313645                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          43468                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses           6215                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51908.527755                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.815768                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    322611500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51889.300080                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency    322492000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses             6215                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    248617500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency    248616500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses         6215                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses          147714                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_hits              147714                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.636939                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.637249                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             282116                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52326.169359                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.293792                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  95069                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     9787453000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.663015                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               187047                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses             282168                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52405.047421                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.304492                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                  95122                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     9802154500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.662889                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               187046                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   7482122000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.663015                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          187047                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   7482084000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.662889                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          187046                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.083104                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.474046                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2723.143012                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15533.530659                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            282116                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52326.169359                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.293792                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.083128                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.473986                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2723.922410                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15531.583322                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            282168                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52405.047421                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.304492                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 95069                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    9787453000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.663015                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              187047                       # number of overall misses
+system.cpu.l2cache.overall_hits                 95122                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    9802154500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.662889                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              187046                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   7482122000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.663015                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         187047                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   7482084000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.662889                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         187046                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                147732                       # number of replacements
-system.cpu.l2cache.sampled_refs                172938                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                147731                       # number of replacements
+system.cpu.l2cache.sampled_refs                172937                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18256.673671                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  110151                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18255.505732                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  110204                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                  120636                       # number of writebacks
-system.cpu.numCycles                        211756614                       # number of cpu cycles simulated
-system.cpu.runCycles                        181197969                       # Number of cycles cpu stages are processed.
+system.cpu.numCycles                        210104718                       # number of cpu cycles simulated
+system.cpu.runCycles                        177818547                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles               113080171                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                 98676443                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              46.598990                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles               123406302                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                 88350312                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              41.722575                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles               121940828                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles               113077434                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles                 97027284                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization              46.180440                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles               121740642                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles                 88364076                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization              42.057159                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles               120288932                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-2.runCycles                 89815786                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              42.414631                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles               176525344                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization              42.748105                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles               174873448                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-3.runCycles                 35231270                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              16.637624                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles               123415941                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization              16.768434                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles               121764045                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-4.runCycles                 88340673                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              41.718023                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles                     211756614                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization              42.046021                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles                     210104718                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------