diff options
| author | Kevin Lim <ktlim@umich.edu> | 2007-04-27 14:35:58 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2007-04-27 14:35:58 -0400 |
| commit | 7f39291c81cb65dc166926136c8f3cab253df160 (patch) | |
| tree | 8e2ef8eb5b3d3a092025a2a390be07cfc2e3c25b /tests/long/50.vortex/ref/alpha | |
| parent | 522e59840f2d3c44d7d95ebc44b44abebb1212c9 (diff) | |
| download | gem5-7f39291c81cb65dc166926136c8f3cab253df160.tar.xz | |
Update Alpha reference stats for clock changes.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
Update refs for clock changes.
--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
Diffstat (limited to 'tests/long/50.vortex/ref/alpha')
12 files changed, 378 insertions, 477 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index d565e945f..6aa726853 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 85be70a92..e22560975 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 00598f40d..91b29d8d9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 7945230 # Number of BTB hits -global.BPredUnit.BTBLookups 13714223 # Number of BTB lookups -global.BPredUnit.RASInCorrect 29001 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454297 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10141226 # Number of conditional branches predicted -global.BPredUnit.lookups 15617287 # Number of BP lookups -global.BPredUnit.usedRAS 1851141 # Number of times the RAS was used to get a target. -host_inst_rate 91600 # Simulator instruction rate (inst/s) -host_mem_usage 155864 # Number of bytes of host memory used -host_seconds 868.91 # Real time elapsed on the host -host_tick_rate 1051887 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 16262618 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 12842437 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22199501 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16236124 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7744324 # Number of BTB hits +global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups +global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted +global.BPredUnit.lookups 15489897 # Number of BP lookups +global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target. +host_inst_rate 108228 # Simulator instruction rate (inst/s) +host_mem_usage 159488 # Number of bytes of host memory used +host_seconds 735.41 # Real time elapsed on the host +host_tick_rate 23792996 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.000914 # Number of seconds simulated -sim_ticks 913992014 # Number of ticks simulated +sim_seconds 0.017498 # Number of seconds simulated +sim_ticks 17497602000 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3798224 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 61093189 +system.cpu.commit.COM:committed_per_cycle.samples 33996100 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 33945527 5556.35% - 1 9263496 1516.29% - 2 5234944 856.88% - 3 3369457 551.53% - 4 2068681 338.61% - 5 1423240 232.96% - 6 1205139 197.26% - 7 784481 128.41% - 8 3798224 621.71% + 0 8358440 2458.65% + 1 8230566 2421.03% + 2 4712162 1386.09% + 3 3108634 914.41% + 4 2121957 624.18% + 5 1131901 332.95% + 6 1374606 404.34% + 7 697761 205.25% + 8 4260073 1253.11% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 359791 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8215609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 11.483501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 11.483501 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19669616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4470.389268 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.793422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19511676 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 706053281 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.008030 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 157940 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 96341 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 199629634 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003132 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61599 # number of ReadReq MSHR misses +system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9707.501078 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9477.511675 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13569879 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10129757960 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071407 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1043498 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900030 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1359719645 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143468 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3321.963636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3975 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 161.320715 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 365416 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 3975 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34282993 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9019.034891 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33081555 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10835811241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.035045 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1201438 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 996371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1559349279 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005982 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205067 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses +system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34282993 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9019.034891 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33081555 # number of overall hits -system.cpu.dcache.overall_miss_latency 10835811241 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.035045 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1201438 # number of overall misses -system.cpu.dcache.overall_mshr_hits 996371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1559349279 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005982 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205067 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33236178 # number of overall hits +system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses +system.cpu.dcache.overall_misses 980372 # number of overall misses +system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200971 # number of replacements -system.cpu.dcache.sampled_refs 205067 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 201077 # number of replacements +system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4063.517542 # Cycle average of tags in use -system.cpu.dcache.total_refs 33081555 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 17025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147753 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 13116101 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95141 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3521692 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 99189601 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 29616630 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 18020228 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1276894 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 291919 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 340231 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 15617287 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13002150 # Number of cache lines fetched -system.cpu.fetch.Cycles 31529148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 124397 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 100725428 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 547316 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.250397 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13002150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9796371 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.614964 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use +system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147781 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched +system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 62370084 +system.cpu.fetch.rateDist.samples 34995208 system.cpu.fetch.rateDist.min_value 0 - 0 43843090 7029.51% - 1 1383259 221.78% - 2 1262238 202.38% - 3 1426265 228.68% - 4 3918105 628.20% - 5 1724208 276.45% - 6 613107 98.30% - 7 1031700 165.42% - 8 7168112 1149.29% + 0 16625619 4750.83% + 1 1365816 390.29% + 2 1258616 359.65% + 3 1410956 403.19% + 4 3900976 1114.72% + 5 1678758 479.71% + 6 612174 174.93% + 7 1011089 288.92% + 8 7131204 2037.77% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13002150 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3387.778909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2412.580892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12899943 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 346254719 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.007861 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 102207 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 14535 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 211515792 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006743 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 87672 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5804 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 147.140366 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 5804 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13002150 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3387.778909 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency -system.cpu.icache.demand_hits 12899943 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 346254719 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.007861 # miss rate for demand accesses -system.cpu.icache.demand_misses 102207 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 14535 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 211515792 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006743 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 87672 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency +system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses +system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13002150 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3387.778909 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12899943 # number of overall hits -system.cpu.icache.overall_miss_latency 346254719 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.007861 # miss rate for overall accesses -system.cpu.icache.overall_misses 102207 # number of overall misses -system.cpu.icache.overall_mshr_hits 14535 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 211515792 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006743 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 87672 # number of overall MSHR misses +system.cpu.icache.overall_hits 12690553 # number of overall hits +system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses +system.cpu.icache.overall_misses 87520 # number of overall misses +system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 85624 # number of replacements -system.cpu.icache.sampled_refs 87671 # Sample count of references to valid blocks. +system.cpu.icache.replacements 84818 # number of replacements +system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1862.743229 # Cycle average of tags in use -system.cpu.icache.total_refs 12899943 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use +system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 851621931 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14377755 # Number of branches executed -system.cpu.iew.EXEC:nop 9220461 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.335296 # Inst execution rate -system.cpu.iew.EXEC:refs 36382036 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15204952 # Number of stores executed +system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14304724 # Number of branches executed +system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed +system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate +system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15116998 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 46748099 # num instructions consuming a value -system.cpu.iew.WB:count 82847738 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.736514 # average fanout of values written-back +system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value +system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 34430613 # num instructions producing a value -system.cpu.iew.WB:rate 1.328325 # insts written-back per cycle -system.cpu.iew.WB:sent 82914162 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 396555 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4917376 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22199501 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4762 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 311974 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16236124 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 96553237 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21177084 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 433562 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 83282498 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 37202 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32801872 # num instructions producing a value +system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle +system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11594 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1276894 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 204710 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 98563 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1300046 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1230 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 27684 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1255 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1820102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1391505 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 27684 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103251 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 293304 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.087081 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.087081 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 83716060 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 46816661 55.92% # Type of FU issued - IntMult 44502 0.05% # Type of FU issued + IntAlu 46687810 55.95% # Type of FU issued + IntMult 45238 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 125345 0.15% # Type of FU issued - FloatCmp 86 0.00% # Type of FU issued - FloatCvt 122997 0.15% # Type of FU issued - FloatMult 51 0.00% # Type of FU issued - FloatDiv 37854 0.05% # Type of FU issued + FloatAdd 120004 0.14% # Type of FU issued + FloatCmp 87 0.00% # Type of FU issued + FloatCvt 122290 0.15% # Type of FU issued + FloatMult 50 0.00% # Type of FU issued + FloatDiv 37770 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21285503 25.43% # Type of FU issued - MemWrite 15283061 18.26% # Type of FU issued + MemRead 21206489 25.41% # Type of FU issued + MemWrite 15228353 18.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1123822 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013424 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 98385 8.75% # attempts to use FU when none available + IntAlu 169452 11.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 476117 42.37% # attempts to use FU when none available - MemWrite 549320 48.88% # attempts to use FU when none available + MemRead 649726 45.68% # attempts to use FU when none available + MemWrite 603028 42.40% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 62370084 +system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 25315225 4058.87% - 1 13800975 2212.76% - 2 10743054 1722.47% - 3 5596398 897.29% - 4 4388925 703.69% - 5 1495414 239.76% - 6 664039 106.47% - 7 305653 49.01% - 8 60401 9.68% + 0 5876071 1679.11% + 1 8518834 2434.29% + 2 6419045 1834.26% + 3 4436708 1267.80% + 4 4423684 1264.08% + 5 2554091 729.84% + 6 1512126 432.10% + 7 794096 226.92% + 8 460553 131.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.342247 # Inst issue rate -system.cpu.iq.iqInstsAdded 87328014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 83716060 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4762 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7507881 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 113500 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6033024 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 292729 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7766.621627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2997.837795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 123055 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1317793758 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.579628 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169674 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 508655130 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579628 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169674 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147285 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003167 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 468 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003167 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 468 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate +system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.593300 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 292729 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7766.621627 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 123055 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1317793758 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.579628 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169674 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 508655130 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.579628 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169674 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440482 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7745.258419 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 270340 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1317793758 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.386263 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170142 # number of overall misses +system.cpu.l2cache.overall_hits 269574 # number of overall hits +system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170199 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 508655130 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385201 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169674 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136905 # number of replacements -system.cpu.l2cache.sampled_refs 169673 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136967 # number of replacements +system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30821.723437 # Cycle average of tags in use -system.cpu.l2cache.total_refs 270340 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 468003000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115935 # number of writebacks -system.cpu.numCycles 62370084 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8787185 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use +system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115938 # number of writebacks +system.cpu.numCycles 34995208 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 113083 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 30263464 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3026568 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 587 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 118807787 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 98380136 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 59048113 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 17777635 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1276894 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3354217 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 6501232 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 910689 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4741 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5955323 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4739 # count of temporary serializing insts renamed -system.cpu.timesIdled 280733 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed +system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg index 327142d7c..472b08431 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg @@ -134,7 +134,7 @@ DB Handle Chunk's StackPtr = 20797 DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 40054800 + KERNEL in CORE[ 1] Restored @ 4005c800 OPEN File ./input/lendian.wnv *Status = 0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 179e8ea77..57d9578d2 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,11 +33,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index 725aaed50..fbb08bf4b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 9c60e1316..8a03d8929 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1347543 # Simulator instruction rate (inst/s) -host_mem_usage 179988 # Number of bytes of host memory used -host_seconds 65.56 # Real time elapsed on the host -host_tick_rate 1347535 # Simulator tick rate (ticks/s) +host_inst_rate 842354 # Simulator instruction rate (inst/s) +host_mem_usage 152996 # Number of bytes of host memory used +host_seconds 104.87 # Real time elapsed on the host +host_tick_rate 421175511 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 88340673 # Number of ticks simulated +sim_seconds 0.044170 # Number of seconds simulated +sim_ticks 44170336500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 88340674 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 0e1a3c9f1..2f49c7692 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index 0dc85858d..c1faaa3e6 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 9a9778162..939083267 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 704446 # Simulator instruction rate (inst/s) -host_mem_usage 275648 # Number of bytes of host memory used -host_seconds 125.40 # Real time elapsed on the host -host_tick_rate 9716991 # Simulator tick rate (ticks/s) +host_inst_rate 562157 # Simulator instruction rate (inst/s) +host_mem_usage 158620 # Number of bytes of host memory used +host_seconds 157.15 # Real time elapsed on the host +host_tick_rate 396922606 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.001219 # Number of seconds simulated -sim_ticks 1218558003 # Number of ticks simulated +sim_seconds 0.062375 # Number of seconds simulated +sim_ticks 62374966500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3130.058422 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2130.058422 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 190198000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 129433000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3436.431765 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2436.431765 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 493396000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 349818000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3345.326241 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 683594000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 479251000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3345.326241 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 683594000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 479251000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4082.118898 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 307192000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 2831.355644 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1831.355644 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 216417500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 139981500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 2831.355644 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 216417500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 139981500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 2831.355644 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 216417500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 139981500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1880.010701 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2532.769537 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1531.091909 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 427222500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 258261521 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.002965 # mi system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2532.769537 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 427222500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 258261521 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2526.209820 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 427222500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 258261521 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 135910 # number of replacements system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32002.173981 # Cycle average of tags in use system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 30452104000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.numCycles 62374966500 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. |