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authorSteve Reinhardt <stever@gmail.com>2008-02-16 14:58:37 -0500
committerSteve Reinhardt <stever@gmail.com>2008-02-16 14:58:37 -0500
commit3204f968091d32846a59c0666157c6c8946842d1 (patch)
tree497c84fa2634b7bcd6c0a5ab03e6d602c264fd07 /tests/long/50.vortex/ref/alpha
parent4597a71cef808969c442fca73ae662efe75550d7 (diff)
downloadgem5-3204f968091d32846a59c0666157c6c8946842d1.tar.xz
Update stats for new writeback behavior.
--HG-- extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
Diffstat (limited to 'tests/long/50.vortex/ref/alpha')
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt611
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini1
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt131
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr1
4 files changed, 370 insertions, 374 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
index 74d2aee08..8d53ad02b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 8036279 # Number of BTB hits
-global.BPredUnit.BTBLookups 14260181 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 35537 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 456495 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 10555311 # Number of conditional branches predicted
-global.BPredUnit.lookups 16250871 # Number of BP lookups
-global.BPredUnit.usedRAS 1941181 # Number of times the RAS was used to get a target.
-host_inst_rate 115474 # Simulator instruction rate (inst/s)
-host_mem_usage 160356 # Number of bytes of host memory used
-host_seconds 689.26 # Real time elapsed on the host
-host_tick_rate 36122153 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12102830 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 10931763 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 22978723 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16295551 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 8038204 # Number of BTB hits
+global.BPredUnit.BTBLookups 14256935 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 35926 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 456185 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 10553314 # Number of conditional branches predicted
+global.BPredUnit.lookups 16248074 # Number of BP lookups
+global.BPredUnit.usedRAS 1941559 # Number of times the RAS was used to get a target.
+host_inst_rate 107979 # Simulator instruction rate (inst/s)
+host_mem_usage 171824 # Number of bytes of host memory used
+host_seconds 737.10 # Real time elapsed on the host
+host_tick_rate 33795098 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 12328057 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 11324911 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 22967030 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16293172 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.024898 # Number of seconds simulated
-sim_ticks 24897604000 # Number of ticks simulated
+sim_seconds 0.024910 # Number of seconds simulated
+sim_ticks 24910446000 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3356243 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 3431451 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 48528188
+system.cpu.commit.COM:committed_per_cycle.samples 48556236
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 19702397 4059.99%
- 1 10946158 2255.63%
- 2 5036045 1037.76%
- 3 3466785 714.39%
- 4 2664416 549.05%
- 5 1534889 316.29%
- 6 1008769 207.87%
- 7 812486 167.43%
- 8 3356243 691.61%
+ 0 19632028 4043.15%
+ 1 11130407 2292.27%
+ 2 5090838 1048.44%
+ 3 3451952 710.92%
+ 4 2493473 513.52%
+ 5 1522245 313.50%
+ 6 990886 204.07%
+ 7 812956 167.43%
+ 8 3431451 706.70%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 360762 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 360457 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 8068812 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8047613 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.625633 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.625633 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 20378393 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15241.304772 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4212.764920 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20316865 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 937767000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.003019 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 61528 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 82787 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 259203000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003019 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61528 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 13782122 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32047.161184 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5374.422625 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13632306 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4801177500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010870 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 149816 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 831255 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 805174500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010870 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149816 # number of WriteReq MSHR misses
+system.cpu.cpi 0.625955 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.625955 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 20358815 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14848.430668 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3932.171708 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20297292 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 913520000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.003022 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 61523 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 82415 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 241919000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61523 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 13806620 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 30619.646254 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5319.309194 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13656795 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4587588500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 149825 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 806757 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 796965500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 149825 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 165.626302 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 165.649492 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34160515 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27154.518226 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 5036.232398 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33949171 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5738944500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006187 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 211344 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 914042 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1064377500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006187 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 211344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 34165435 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 26028.675455 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33954087 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 5501108500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.006186 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 889172 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 1038884500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.006186 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34160515 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27154.518226 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 5036.232398 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 34165435 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 26028.675455 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33949171 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5738944500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006187 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 211344 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 914042 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1064377500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006187 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 211344 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 33954087 # number of overall hits
+system.cpu.dcache.overall_miss_latency 5501108500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.006186 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 211348 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 889172 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 1038884500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.006186 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 200917 # number of replacements
-system.cpu.dcache.sampled_refs 205013 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 200918 # number of replacements
+system.cpu.dcache.sampled_refs 205014 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4080.927145 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33955545 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 120649000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147757 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 943541 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 96612 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3650840 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 101683737 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 27936407 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 19620838 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1265214 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 284149 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 27403 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 36632249 # DTB accesses
-system.cpu.dtb.acv 36 # DTB access violations
-system.cpu.dtb.hits 36460811 # DTB hits
-system.cpu.dtb.misses 171438 # DTB misses
-system.cpu.dtb.read_accesses 21568197 # DTB read accesses
-system.cpu.dtb.read_acv 34 # DTB read access violations
-system.cpu.dtb.read_hits 21411149 # DTB read hits
-system.cpu.dtb.read_misses 157048 # DTB read misses
-system.cpu.dtb.write_accesses 15064052 # DTB write accesses
+system.cpu.dcache.tagsinuse 4080.935098 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33960465 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 120644000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147759 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 965138 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 96643 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3649464 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 101643368 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 27939518 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 19626008 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1262570 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 284543 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 25573 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 36605590 # DTB accesses
+system.cpu.dtb.acv 38 # DTB access violations
+system.cpu.dtb.hits 36432080 # DTB hits
+system.cpu.dtb.misses 173510 # DTB misses
+system.cpu.dtb.read_accesses 21546917 # DTB read accesses
+system.cpu.dtb.read_acv 36 # DTB read access violations
+system.cpu.dtb.read_hits 21390081 # DTB read hits
+system.cpu.dtb.read_misses 156836 # DTB read misses
+system.cpu.dtb.write_accesses 15058673 # DTB write accesses
system.cpu.dtb.write_acv 2 # DTB write access violations
-system.cpu.dtb.write_hits 15049662 # DTB write hits
-system.cpu.dtb.write_misses 14390 # DTB write misses
-system.cpu.fetch.Branches 16250871 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 13378376 # Number of cache lines fetched
-system.cpu.fetch.Cycles 33230958 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 152674 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 103283004 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 574326 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.326354 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 13378376 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 9977460 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.074155 # Number of inst fetches per cycle
+system.cpu.dtb.write_hits 15041999 # DTB write hits
+system.cpu.dtb.write_misses 16674 # DTB write misses
+system.cpu.fetch.Branches 16248074 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13374991 # Number of cache lines fetched
+system.cpu.fetch.Cycles 33229665 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 154532 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 103238390 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 573003 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.326130 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 13374991 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 9979763 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.072191 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 49793403
+system.cpu.fetch.rateDist.samples 49818807
system.cpu.fetch.rateDist.min_value 0
- 0 29966239 6018.11%
- 1 1875035 376.56%
- 2 1535605 308.40%
- 3 1804270 362.35%
- 4 3961078 795.50%
- 5 1877676 377.09%
- 6 698372 140.25%
- 7 1099999 220.91%
- 8 6975129 1400.81%
+ 0 29989736 6019.76%
+ 1 1895135 380.41%
+ 2 1526458 306.40%
+ 3 1823774 366.08%
+ 4 3936760 790.22%
+ 5 1866062 374.57%
+ 6 698148 140.14%
+ 7 1109093 222.63%
+ 8 6973641 1399.80%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 13377544 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 4583.036351 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2544.804459 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 13291961 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 392230000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 85583 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 832 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 217792000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.006398 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 85583 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 13374115 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4650.026870 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2608.921937 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 13288517 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 398033000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.006400 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 85598 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 876 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 223318500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.006400 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 85598 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 155.310763 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 155.243312 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 13377544 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 4583.036351 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2544.804459 # average overall mshr miss latency
-system.cpu.icache.demand_hits 13291961 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 392230000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.006398 # miss rate for demand accesses
-system.cpu.icache.demand_misses 85583 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 832 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 217792000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.006398 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 85583 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 13374115 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4650.026870 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency
+system.cpu.icache.demand_hits 13288517 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 398033000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.006400 # miss rate for demand accesses
+system.cpu.icache.demand_misses 85598 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 876 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 223318500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.006400 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 85598 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 13377544 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 4583.036351 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2544.804459 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 13374115 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4650.026870 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 13291961 # number of overall hits
-system.cpu.icache.overall_miss_latency 392230000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.006398 # miss rate for overall accesses
-system.cpu.icache.overall_misses 85583 # number of overall misses
-system.cpu.icache.overall_mshr_hits 832 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 217792000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.006398 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 85583 # number of overall MSHR misses
+system.cpu.icache.overall_hits 13288517 # number of overall hits
+system.cpu.icache.overall_miss_latency 398033000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.006400 # miss rate for overall accesses
+system.cpu.icache.overall_misses 85598 # number of overall misses
+system.cpu.icache.overall_mshr_hits 876 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 223318500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.006400 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 85598 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 83535 # number of replacements
-system.cpu.icache.sampled_refs 85583 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 83550 # number of replacements
+system.cpu.icache.sampled_refs 85598 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1922.482733 # Cycle average of tags in use
-system.cpu.icache.total_refs 13291961 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 21658930000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tagsinuse 1922.621732 # Cycle average of tags in use
+system.cpu.icache.total_refs 13288517 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 21667252000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1806 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14744087 # Number of branches executed
-system.cpu.iew.EXEC:nop 9381144 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.703621 # Inst execution rate
-system.cpu.iew.EXEC:refs 36974156 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15296705 # Number of stores executed
+system.cpu.idleCycles 2086 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14743916 # Number of branches executed
+system.cpu.iew.EXEC:nop 9378551 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.702006 # Inst execution rate
+system.cpu.iew.EXEC:refs 36947583 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15291466 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 42381395 # num instructions consuming a value
-system.cpu.iew.WB:count 84348023 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.765304 # average fanout of values written-back
+system.cpu.iew.WB:consumers 42399540 # num instructions consuming a value
+system.cpu.iew.WB:count 84317145 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.765160 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 32434648 # num instructions producing a value
-system.cpu.iew.WB:rate 1.693898 # insts written-back per cycle
-system.cpu.iew.WB:sent 84580813 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 401245 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 18721 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 22978723 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 359067 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16295551 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 98839523 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 21677451 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 547314 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 84832143 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 2010 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 32442413 # num instructions producing a value
+system.cpu.iew.WB:rate 1.692405 # insts written-back per cycle
+system.cpu.iew.WB:sent 84551587 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 401023 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 18086 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 22967030 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 4976 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 358113 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 16293172 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 98809667 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 21656117 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 536500 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 84795443 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1943 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 182 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1265214 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 2634 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 166 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1262570 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 2513 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 948620 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 989 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 947497 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 960 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 20664 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1306 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2599324 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1450932 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 20664 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 108416 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 292829 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.598382 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.598382 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 85379457 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 18554 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1310 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 2587631 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1448553 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 18554 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 108095 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 292928 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.597558 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.597558 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 85331943 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 47888413 56.09% # Type of FU issued
- IntMult 42937 0.05% # Type of FU issued
+ IntAlu 47873863 56.10% # Type of FU issued
+ IntMult 42967 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 121447 0.14% # Type of FU issued
+ FloatAdd 121266 0.14% # Type of FU issued
FloatCmp 86 0.00% # Type of FU issued
- FloatCvt 122009 0.14% # Type of FU issued
+ FloatCvt 121911 0.14% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued
- FloatDiv 38531 0.05% # Type of FU issued
+ FloatDiv 38525 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 21786877 25.52% # Type of FU issued
- MemWrite 15379107 18.01% # Type of FU issued
+ MemRead 21762707 25.50% # Type of FU issued
+ MemWrite 15370568 18.01% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 969118 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011351 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 973739 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011411 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 94143 9.71% # attempts to use FU when none available
+ IntAlu 95466 9.80% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -311,105 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 449697 46.40% # attempts to use FU when none available
- MemWrite 425278 43.88% # attempts to use FU when none available
+ MemRead 447999 46.01% # attempts to use FU when none available
+ MemWrite 430274 44.19% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 49793403
+system.cpu.iq.ISSUE:issued_per_cycle.samples 49818807
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 14936070 2999.61%
- 1 13322790 2675.61%
- 2 8095375 1625.79%
- 3 4742465 952.43%
- 4 4697667 943.43%
- 5 2107602 423.27%
- 6 1178715 236.72%
- 7 464198 93.22%
- 8 248521 49.91%
+ 0 14814928 2973.76%
+ 1 13524369 2714.71%
+ 2 8025078 1610.85%
+ 3 4803693 964.23%
+ 4 4680291 939.46%
+ 5 2123644 426.27%
+ 6 1156346 232.11%
+ 7 454785 91.29%
+ 8 235673 47.31%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.714612 # Inst issue rate
-system.cpu.iq.iqInstsAdded 89453393 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 85379457 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9664351 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 49402 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 6605234 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 13403794 # ITB accesses
+system.cpu.iq.ISSUE:rate 1.712774 # Inst issue rate
+system.cpu.iq.iqInstsAdded 89426140 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 85331943 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 4976 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 9626821 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 45871 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 393 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 6618385 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 13400594 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 13378376 # ITB hits
-system.cpu.itb.misses 25418 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 143485 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 4092.825034 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2092.825034 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 587259000 # number of ReadExReq miss cycles
+system.cpu.itb.hits 13374991 # ITB hits
+system.cpu.itb.misses 25603 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 143491 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 4105.274895 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2105.274895 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 589070000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143485 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 300289000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 143491 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 302088000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143485 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 147111 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4141.158104 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2141.158104 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 98428 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 201604000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.330927 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 48683 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 104238000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.330927 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 48683 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6350 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 4242.677165 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2244.724409 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 26941000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses 143491 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 147121 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4130.611741 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2130.611741 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 102527 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 184200500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.303111 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 44594 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 95012500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303111 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 44594 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 6346 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4217.538607 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.593760 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 26764500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6350 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14254000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 6346 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14231500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6350 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147757 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 147757 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 147757 # number of Writeback MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 6346 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147759 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147759 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.449601 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.676534 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 290596 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4105.069523 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2105.069523 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 98428 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 788863000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.661289 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 192168 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 290612 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4111.282133 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 102527 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 773270500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.647203 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 188085 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 404527000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.661289 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 192168 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 397100500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.647203 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 188085 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 290596 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4105.069523 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2105.069523 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 290612 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4111.282133 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 98428 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 788863000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.661289 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 192168 # number of overall misses
+system.cpu.l2cache.overall_hits 102527 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 773270500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.647203 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 188085 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 404527000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.661289 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 192168 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 397100500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.647203 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 188085 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -421,31 +418,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 25961 # number of replacements
-system.cpu.l2cache.sampled_refs 41866 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 148798 # number of replacements
+system.cpu.l2cache.sampled_refs 174015 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 4585.787881 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 102555 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18438.001925 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 117727 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 49795209 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 258129 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 120645 # number of writebacks
+system.cpu.numCycles 49820893 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 263970 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 32247 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 28248638 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 541903 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 121528434 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 100873332 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 60701342 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 19331218 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1265214 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 614234 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 8154461 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 75970 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 5252 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 1383660 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 5250 # count of temporary serializing insts renamed
-system.cpu.timesIdled 679 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 36282 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 28255906 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 551452 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 121470810 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 100830627 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 60670426 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 19329077 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1262570 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 631100 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 8123545 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 76184 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 5248 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1415098 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 5246 # count of temporary serializing insts renamed
+system.cpu.timesIdled 786 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 99534f902..0e853bbc7 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -169,6 +169,7 @@ euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
+max_stack_size=67108864
output=cout
pid=100
ppid=99
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
index c05407db8..5c61eb239 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,21 +1,21 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1210019 # Simulator instruction rate (inst/s)
-host_mem_usage 209960 # Number of bytes of host memory used
-host_seconds 73.01 # Real time elapsed on the host
-host_tick_rate 1768843958 # Simulator tick rate (ticks/s)
+host_inst_rate 826490 # Simulator instruction rate (inst/s)
+host_mem_usage 170652 # Number of bytes of host memory used
+host_seconds 106.89 # Real time elapsed on the host
+host_tick_rate 1207717238 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.129140 # Number of seconds simulated
-sim_ticks 129139604000 # Number of ticks simulated
+sim_seconds 0.129089 # Number of seconds simulated
+sim_ticks 129089084000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 19821.229326 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17821.229326 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1273533000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1204437000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1152003000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1082907000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 23833.613541 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 23505.456929 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 21505.456929 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5018358000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 4949262000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4597242000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 4528146000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 23833.613541 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 23505.456929 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 21505.456929 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34679457 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5018358000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 4949262000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
system.cpu.dcache.overall_misses 210558 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4597242000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 4528146000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 200247 # number of replacements
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4080.930479 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4080.925680 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 737173000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 736945000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.dtb.accesses 34987415 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 14374.483228 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12374.483228 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 1098728000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 945856000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 14374.483228 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12374.483228 # average overall mshr miss latency
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 1098728000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 945856000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 14374.483228 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12374.483228 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 88361638 # number of overall hits
-system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 1098728000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_misses 76436 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 945856000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1876.941758 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1876.966161 # Cycle average of tags in use
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -171,30 +171,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 143578 # nu
system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 89695 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1045132000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.346251 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 47506 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 522566000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.346251 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 47506 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 952512000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 21989.380531 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 21869.026549 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 136664000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 135916000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 147714 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 147714 # number of Writeback MSHR misses
+system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.294067 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
@@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 89695 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 4203848000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.680549 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 191084 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 4111228000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2101924000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.680549 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 191084 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 280779 # nu
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 89695 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 4203848000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.680549 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 191084 # number of overall misses
+system.cpu.l2cache.overall_hits 93905 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 4111228000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 186874 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2101924000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.680549 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 191084 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 24953 # number of replacements
-system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 147560 # number of replacements
+system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 4393.054480 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18266.602159 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.l2cache.writebacks 120634 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 258279208 # number of cpu cycles simulated
+system.cpu.numCycles 258178168 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
index f33d007a7..5992f7131 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
@@ -1,2 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.