Stats: Re update stats.

4 files changed, 46 insertions, 13 deletions

diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 1d235cb1e..0e5c2c18c 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
index eabe42249..e391217dd 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 8e789b6bf..54e01817e 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:37:39
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+M5 compiled Feb  7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 595ab3b43..b20318b2f 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 607999                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 269484                       # Number of bytes of host memory used
-host_seconds                                   161.18                       # Real time elapsed on the host
-host_tick_rate                              825650483                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 430473                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 244816                       # Number of bytes of host memory used
+host_seconds                                   227.65                       # Real time elapsed on the host
+host_tick_rate                              584574230                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    97997303                       # Number of instructions simulated
 sim_seconds                                  0.133079                       # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                   88450                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        266157390                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                  266157390                       # Number of busy cycles
+system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_fp_insts                            56                       # number of float instructions
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                         97997303                       # Number of instructions executed
-system.cpu.num_refs                          47871034                       # Number of memory references
+system.cpu.num_int_alu_accesses              89710267                       # Number of integer alu accesses
+system.cpu.num_int_insts                     89710267                       # number of integer instructions
+system.cpu.num_int_register_reads           285424208                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           73333595                       # number of times the integer registers were written
+system.cpu.num_load_insts                    27315295                       # Number of load instructions
+system.cpu.num_mem_refs                      47871034                       # number of memory refs
+system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------