tests: update stats for name changes

3 files changed, 15 insertions, 15 deletions

diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index c681e2402..8d849c15a 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index b08e3aaf1..7b793d7b7 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:45:50
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:20:07
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 0bdccd82b..4142f5d9a 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 558313                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262448                       # Number of bytes of host memory used
-host_seconds                                   178.74                       # Real time elapsed on the host
-host_tick_rate                              744762819                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2031292                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 221580                       # Number of bytes of host memory used
+host_seconds                                    49.13                       # Real time elapsed on the host
+host_tick_rate                             2709639216                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    99791663                       # Number of instructions simulated
 sim_seconds                                  0.133117                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses           159998                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995345                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses            18908                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.847746                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses          133917                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.066099                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.489066                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes           73126599                       # nu
 system.cpu.num_load_insts                    27307109                       # Number of load instructions
 system.cpu.num_mem_refs                      47862848                       # number of memory refs
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------