diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-29 00:00:26 -0800 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-29 00:00:26 -0800 |
commit | fa5e3b47c8d541259438c5177ef57232f5317907 (patch) | |
tree | 55a6a447319c0aacfc3565a82bf622c4f92f959b /tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt | |
parent | 16e99e4677c24147e09ff10d375751a7b114a8d7 (diff) | |
download | gem5-fa5e3b47c8d541259438c5177ef57232f5317907.tar.xz |
SPARC: Fix the initial stack to match what the Linux kernel does.
--HG--
extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
Diffstat (limited to 'tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt')
-rw-r--r-- | tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt | 178 |
1 files changed, 89 insertions, 89 deletions
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index d71b47454..a58ca9014 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1846845 # Simulator instruction rate (inst/s) -host_mem_usage 192856 # Number of bytes of host memory used -host_seconds 73.72 # Real time elapsed on the host -host_tick_rate 2717419538 # Simulator tick rate (ticks/s) +host_inst_rate 1907380 # Simulator instruction rate (inst/s) +host_mem_usage 192852 # Number of bytes of host memory used +host_seconds 71.38 # Real time elapsed on the host +host_tick_rate 2806502009 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136141055 # Number of instructions simulated -sim_seconds 0.200317 # Number of seconds simulated -sim_ticks 200316584000 # Number of ticks simulated +sim_insts 136139203 # Number of instructions simulated +sim_seconds 0.200315 # Number of seconds simulated +sim_ticks 200314732000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 964329000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 21198.421943 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19198.421943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 964507000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 873351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 873509000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency @@ -31,13 +31,13 @@ system.cpu.dcache.SwapReq_mshr_misses 40 # nu system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20754892 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2735300000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2735125000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 109412 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2516476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2516315000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 109412 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. @@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23883.829026 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency -system.cpu.dcache.demand_hits 57940704 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3699629000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 23883.385839 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21883.385839 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3699632000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses -system.cpu.dcache.demand_misses 154901 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3389827000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3389824000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 154901 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23883.829026 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 23883.385839 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21883.385839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 57940704 # number of overall hits -system.cpu.dcache.overall_miss_latency 3699629000 # number of overall miss cycles +system.cpu.dcache.overall_hits 57940701 # number of overall hits +system.cpu.dcache.overall_miss_latency 3699632000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses -system.cpu.dcache.overall_misses 154901 # number of overall misses +system.cpu.dcache.overall_misses 154904 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3389827000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3389824000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 154901 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.107113 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.107586 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 584680000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107279 # number of writebacks -system.cpu.icache.ReadReq_accesses 136295664 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.warmup_cycle 584704000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107271 # number of writebacks +system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136108640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses @@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # ms system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.760287 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136295664 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency -system.cpu.icache.demand_hits 136108640 # number of demand (read+write) hits +system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses @@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 187024 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136295664 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136108640 # number of overall hits +system.cpu.icache.overall_hits 136106788 # number of overall hits system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses @@ -148,47 +148,47 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.864278 # Cycle average of tags in use -system.cpu.icache.total_refs 136108640 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 142656863000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 2006.863735 # Cycle average of tags in use +system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 142653354000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2314158000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2313938000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 105189 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1157079000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 105189 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 232513 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 191480 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 902726000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.176476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 41033 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 451363000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 41033 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 4263 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.875205 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 191486 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 902814000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.176486 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 41037 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 451407000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176486 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 41037 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.900609 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 93632000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 93698000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 4263 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46893000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 4263 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 107279 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 107271 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 107279 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 107271 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.315911 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.316385 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -197,14 +197,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 191480 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3216884000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.432991 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 146222 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 191486 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3216752000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.432973 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 146216 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1608442000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.432991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 146222 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1608376000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.432973 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 146216 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -212,14 +212,14 @@ system.cpu.l2cache.overall_accesses 337702 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 191480 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3216884000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.432991 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 146222 # number of overall misses +system.cpu.l2cache.overall_hits 191486 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3216752000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.432973 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 146216 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1608442000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.432991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 146222 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1608376000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.432973 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 146216 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,16 +231,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 22010 # number of replacements -system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 22008 # number of replacements +system.cpu.l2cache.sampled_refs 36484 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6146.948797 # Cycle average of tags in use -system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6146.828377 # Cycle average of tags in use +system.cpu.l2cache.total_refs 193963 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 400633168 # number of cpu cycles simulated -system.cpu.num_insts 136141055 # Number of instructions executed +system.cpu.numCycles 400629464 # number of cpu cycles simulated +system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls |