Very minor regression stats updates due top previous changeset.

Setting dirty bit on swaps added a handful of writebacks in a
few of the longer-running SPARC_SE benchmarks.

2 files changed, 18 insertions, 18 deletions

diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index d6b904f84..397f2cd80 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:30:32
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py long/50.vortex/sparc/linux/simple-timing
+M5 compiled Mar 16 2009 00:51:12
+M5 revision 208de84f046d 6013 default tip
+M5 started Mar 16 2009 00:51:29
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 3d50b13ca..24dff0498 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 683746                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213692                       # Number of bytes of host memory used
-host_seconds                                   199.11                       # Real time elapsed on the host
-host_tick_rate                             1021439068                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1347607                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214288                       # Number of bytes of host memory used
+host_seconds                                   101.02                       # Real time elapsed on the host
+host_tick_rate                             2013168641                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.203377                       # Number of seconds simulated
@@ -80,7 +80,7 @@ system.cpu.dcache.soft_prefetch_mshr_full            0                       # n
 system.cpu.dcache.tagsinuse               4087.609698                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              778280000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   107271                       # number of writebacks
+system.cpu.dcache.writebacks                   107279                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          134553584                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 16936.029600                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600                       # average ReadReq mshr miss latency
@@ -163,11 +163,11 @@ system.cpu.l2cache.UpgradeReq_misses             4266                       # nu
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency    170640000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses         4266                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          107271                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              107271                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses          107279                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              107279                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.433849                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.433874                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
@@ -201,13 +201,13 @@ system.cpu.l2cache.overall_mshr_miss_rate     0.429151                       # m
 system.cpu.l2cache.overall_mshr_misses         144925                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                120486                       # number of replacements
-system.cpu.l2cache.sampled_refs                139196                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                120487                       # number of replacements
+system.cpu.l2cache.sampled_refs                139197                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             19319.557750                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  199586                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             19319.562378                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  199591                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   87413                       # number of writebacks
+system.cpu.l2cache.writebacks                   87414                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        406753384                       # number of cpu cycles simulated
 system.cpu.num_insts                        136139203                       # Number of instructions executed