Make default PhysicalMemory latency slightly more realistic.

Also update stats to reflect change.

4 files changed, 72 insertions, 71 deletions

diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 77a49bdbd..b127e5d20 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -166,6 +166,7 @@ cmd=vortex bendian.raw
 cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
+errout=cerr
 euid=100
 executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
 gid=100
@@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 [system.physmem]
 type=PhysicalMemory
 file=
-latency=1
+latency=30000
 latency_var=0
 null=false
 range=0:134217727
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
index 89c35043c..398922df0 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 809753                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216324                       # Number of bytes of host memory used
-host_seconds                                   168.12                       # Real time elapsed on the host
-host_tick_rate                             1194295397                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1368614                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211448                       # Number of bytes of host memory used
+host_seconds                                    99.47                       # Real time elapsed on the host
+host_tick_rate                             2062044712                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
-sim_seconds                                  0.200790                       # Number of seconds simulated
-sim_ticks                                200790381000                       # Number of ticks simulated
+sim_seconds                                  0.205117                       # Number of seconds simulated
+sim_ticks                                205116920000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               37185802                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency      983722000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     1757210000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                45499                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency    847225000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1620713000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           45499                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency        27000                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        24000                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_hits                  15876                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency        1080000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency        2240000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_rate          0.002513                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_misses                   40                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency       960000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency      2120000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.002513                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_misses              40                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              20754899                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    2953917000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    6126662000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.005244                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              109405                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   2625702000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5798447000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.005244                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         109405                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 25419.866498                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 50895.212519                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                57940701                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      3937639000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency      7883872000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.002666                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                154904                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   3472927000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   7419160000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.002666                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           154904                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 25419.866498                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50895.212519                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               57940701                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     3937639000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency     7883872000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.002666                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               154904                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   3472927000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   7419160000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.002666                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          154904                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 146582                       # number of replacements
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4089.002644                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4087.433110                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              600016000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              821750000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   107271                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          136293812                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14908.771067                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16936.029600                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              136106788                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     2788298000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency     3167444000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.001372                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency   2227226000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency   2606372000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.001372                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           136293812                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14908.771067                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 16936.029600                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               136106788                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      2788298000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency      3167444000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.001372                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   2227226000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   2606372000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.001372                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          136293812                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14908.771067                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 16936.029600                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              136106788                       # number of overall hits
-system.cpu.icache.overall_miss_latency     2788298000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency     3167444000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.001372                       # miss rate for overall accesses
 system.cpu.icache.overall_misses               187024                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   2227226000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   2606372000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.001372                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                 184976                       # number of replacements
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               2006.709249                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               2004.068304                       # Cycle average of tags in use
 system.cpu.icache.total_refs                136106788                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle           143009204000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.warmup_cycle           146097762000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses          105179                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   2419117000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency   5469308000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses            105179                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1156969000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4207160000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       105179                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            232523                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                192777                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     914158000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency    2066792000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.170934                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses               39746                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    437206000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1589840000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.170934                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses          39746                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses           4266                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency     97704000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency    220896000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses             4266                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency     46926000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency    170640000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses         4266                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses          107271                       # number of Writeback accesses(hits+misses)
@@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses             337702                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                 192777                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3333275000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     7536100000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.429151                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses               144925                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   1594175000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   5797000000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.429151                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses          144925                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                192777                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3333275000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency    7536100000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.429151                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses              144925                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   1594175000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   5797000000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.429151                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses         144925                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                120486                       # number of replacements
 system.cpu.l2cache.sampled_refs                139196                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             19341.325901                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             19311.746813                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  199586                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   87413                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        401580762                       # number of cpu cycles simulated
+system.cpu.numCycles                        410233840                       # number of cpu cycles simulated
 system.cpu.num_insts                        136139203                       # Number of instructions executed
 system.cpu.num_refs                          58160249                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
index b5ea49da4..fc5baf4b1 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
@@ -1,4 +1,4 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7007
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
 warn: ignoring syscall time(4026527848, 4026528248, ...)
 warn: ignoring syscall time(4026527400, 1375098, ...)
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
index 592b35b7a..dd1bc90df 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul 21 2008 20:33:06
-M5 started Mon Jul 21 20:36:59 2008
+M5 compiled Aug  2 2008 17:21:13
+M5 started Sat Aug  2 17:28:00 2008
 M5 executing on zizzer
-M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
-M5 commit date Tue Jul 15 14:38:51 2008 -0400
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 200790381000 because target called exit()
+Exiting @ tick 205116920000 because target called exit()