tests: update stats for name changes

5 files changed, 23 insertions, 22 deletions

diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 7f5789393..8359194cf 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:11
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:19:52
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index d6bfda298..25cfa073d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1204089                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 228576                       # Number of bytes of host memory used
-host_seconds                                   113.06                       # Real time elapsed on the host
-host_tick_rate                              602742669                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4754404                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206464                       # Number of bytes of host memory used
+host_seconds                                    28.63                       # Real time elapsed on the host
+host_tick_rate                             2379947985                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.068149                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          113225733                       # nu
 system.cpu.num_load_insts                    37275868                       # Number of load instructions
 system.cpu.num_mem_refs                      58160249                       # number of memory refs
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 8ec9f75ef..4d41b9cb9 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index b27952d03..0a7053375 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:39
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:09
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index eb6eca0bd..f75c53329 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 463084                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 236284                       # Number of bytes of host memory used
-host_seconds                                   293.98                       # Real time elapsed on the host
-host_tick_rate                              690315679                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2437881                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214216                       # Number of bytes of host memory used
+host_seconds                                    55.84                       # Real time elapsed on the host
+host_tick_rate                             3634125508                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.202942                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses           150663                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997953                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4087.617150                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997953                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 49432.508313                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses           187024                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.978868                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           2004.721102                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.978868                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 16930.864488                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
@@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses          140161                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.121030                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.481204                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3965.924560                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15768.107062                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.121030                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.481204                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -228,6 +228,6 @@ system.cpu.num_int_register_writes          113225732                       # nu
 system.cpu.num_load_insts                    37275868                       # Number of load instructions
 system.cpu.num_mem_refs                      58160249                       # number of memory refs
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------