Stats: Update the stats.

--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8

6 files changed, 74 insertions, 50 deletions

diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index da377104f..dcd40ebc7 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=workload
+children=dtb itb tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
+dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -25,11 +27,23 @@ phase=0
 progress_interval=0
 simulate_stalls=false
 system=system
+tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
 dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
+[system.cpu.dtb]
+type=SparcDTB
+size=64
+
+[system.cpu.itb]
+type=SparcITB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
@@ -53,7 +67,7 @@ bus_id=0
 clock=1000
 responder_set=false
 width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
index 9dd2e7465..c76c08dcd 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,18 +1,18 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 672762                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 151516                       # Number of bytes of host memory used
-host_seconds                                   202.52                       # Real time elapsed on the host
-host_tick_rate                              336380340                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1682182                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 185356                       # Number of bytes of host memory used
+host_seconds                                    80.93                       # Real time elapsed on the host
+host_tick_rate                              842064489                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   136246936                       # Number of instructions simulated
-sim_seconds                                  0.068123                       # Number of seconds simulated
-sim_ticks                                 68123467500                       # Number of ticks simulated
+sim_insts                                   136141055                       # Number of instructions simulated
+sim_seconds                                  0.068150                       # Number of seconds simulated
+sim_ticks                                 68149604500                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        136246936                       # number of cpu cycles simulated
-system.cpu.num_insts                        136246936                       # Number of instructions executed
-system.cpu.num_refs                          58111522                       # Number of memory references
+system.cpu.numCycles                        136299210                       # number of cpu cycles simulated
+system.cpu.num_insts                        136141055                       # Number of instructions executed
+system.cpu.num_refs                          58160249                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
index 13addb638..6a817bd73 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 15 2007 13:02:31
-M5 started Tue May 15 16:40:43 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 14 2007 22:48:17
+M5 started Tue Aug 14 23:33:10 2007
+M5 executing on nacho
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 68123467500 because target called exit()
+Exiting @ tick 68149604500 because target called exit()
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 5f9deac8a..1069d2547 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus tracer workload
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
+dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -65,6 +67,10 @@ write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
+[system.cpu.dtb]
+type=SparcDTB
+size=64
+
 [system.cpu.icache]
 type=BaseCache
 addr_range=0:18446744073709551615
@@ -101,6 +107,10 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.itb]
+type=SparcITB
+size=64
+
 [system.cpu.l2cache]
 type=BaseCache
 addr_range=0:18446744073709551615
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
index e924e185b..2bb84bd57 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1128502                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210664                       # Number of bytes of host memory used
-host_seconds                                   120.73                       # Real time elapsed on the host
-host_tick_rate                             1658768570                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 960220                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192724                       # Number of bytes of host memory used
+host_seconds                                   141.78                       # Real time elapsed on the host
+host_tick_rate                             1412855280                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   136246936                       # Number of instructions simulated
-sim_seconds                                  0.200268                       # Number of seconds simulated
-sim_ticks                                200267857000                       # Number of ticks simulated
+sim_insts                                   136141055                       # Number of instructions simulated
+sim_seconds                                  0.200317                       # Number of seconds simulated
+sim_ticks                                200316584000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030                       # average ReadReq mshr miss latency
@@ -86,53 +86,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 146582                       # number of replacements
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4089.106244                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4089.107113                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              584597000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              584680000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   107279                       # number of writebacks
-system.cpu.icache.ReadReq_accesses          136246937                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          136295664                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 13638.549063                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              136059913                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              136108640                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency     2550736000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.001373                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate          0.001372                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_miss_latency   2176688000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001373                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001372                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                 727.499749                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                 727.760287                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           136246937                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           136295664                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 13638.549063                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               136059913                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               136108640                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency      2550736000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.001373                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate           0.001372                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency   2176688000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.001373                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001372                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses          136246937                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses          136295664                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 13638.549063                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              136059913                       # number of overall hits
+system.cpu.icache.overall_hits              136108640                       # number of overall hits
 system.cpu.icache.overall_miss_latency     2550736000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.001373                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate          0.001372                       # miss rate for overall accesses
 system.cpu.icache.overall_misses               187024                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency   2176688000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.001373                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001372                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -148,9 +148,9 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                 184976                       # number of replacements
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               2006.859894                       # Cycle average of tags in use
-system.cpu.icache.total_refs                136059913                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle           142624255000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tagsinuse               2006.864278                       # Cycle average of tags in use
+system.cpu.icache.total_refs                136108640                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle           142656863000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses          105189                       # number of ReadExReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                 22010                       # number of replacements
 system.cpu.l2cache.sampled_refs                 36485                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              6146.860431                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              6146.948797                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  193951                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     200267857000                       # number of cpu cycles simulated
-system.cpu.num_insts                        136246936                       # Number of instructions executed
-system.cpu.num_refs                          58111522                       # Number of memory references
+system.cpu.numCycles                     200316584000                       # number of cpu cycles simulated
+system.cpu.num_insts                        136141055                       # Number of instructions executed
+system.cpu.num_refs                          58160249                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
index 862e98203..e6db66f3d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 12 2007 12:23:15
-M5 started Sun Aug 12 16:52:13 2007
-M5 executing on zeep
+M5 compiled Aug 14 2007 22:48:17
+M5 started Tue Aug 14 23:34:32 2007
+M5 executing on nacho
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 200267857000 because target called exit()
+Exiting @ tick 200316584000 because target called exit()