update all the regresstion tests for release

--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2

8 files changed, 78 insertions, 78 deletions

diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 7932bf16f..da377104f 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -48,6 +48,7 @@ uid=100
 
 [system.membus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
index b69343874..4d97fe26f 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
@@ -20,6 +20,7 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.workload]
 type=LiveProcess
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
index 37d044e8d..9dd2e7465 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 644632                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 151548                       # Number of bytes of host memory used
-host_seconds                                   211.36                       # Real time elapsed on the host
-host_tick_rate                              322315545                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 672762                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 151516                       # Number of bytes of host memory used
+host_seconds                                   202.52                       # Real time elapsed on the host
+host_tick_rate                              336380340                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136246936                       # Number of instructions simulated
 sim_seconds                                  0.068123                       # Number of seconds simulated
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
index 794510e19..13addb638 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 27 2007 14:35:32
-M5 started Fri Apr 27 15:55:23 2007
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 16:40:43 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 1bc14e993..ff1b40886 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -36,8 +36,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -75,8 +74,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -114,8 +112,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=10000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
@@ -171,6 +169,7 @@ uid=100
 
 [system.membus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
index cb469d872..c2fb507ae 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.workload]
 type=LiveProcess
@@ -61,13 +62,14 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.icache]
 type=BaseCache
 size=131072
 assoc=2
 block_size=64
-latency=1
+latency=1000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -98,14 +100,13 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
 [system.cpu.dcache]
 type=BaseCache
 size=262144
 assoc=2
 block_size=64
-latency=1
+latency=1000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -136,14 +137,13 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
 [system.cpu.l2cache]
 type=BaseCache
 size=2097152
 assoc=2
 block_size=64
-latency=1
+latency=10000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -174,5 +174,4 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
index 4e8db9778..bf74220de 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 466766                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 157052                       # Number of bytes of host memory used
-host_seconds                                   291.90                       # Real time elapsed on the host
-host_tick_rate                              335938336                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 480067                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 157016                       # Number of bytes of host memory used
+host_seconds                                   283.81                       # Real time elapsed on the host
+host_tick_rate                              698858124                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136246936                       # Number of instructions simulated
-sim_seconds                                  0.098059                       # Number of seconds simulated
-sim_ticks                                 98059078500                       # Number of ticks simulated
+sim_seconds                                  0.198342                       # Number of seconds simulated
+sim_ticks                                198341876000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3241.706786                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2241.706786                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               37185812                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency      147462000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency      591594000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                45489                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency    101973000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency    546105000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           45489                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency  3166.666667                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency  2166.666667                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        12800                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        11800                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_hits                  15901                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency          47500                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         192000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_rate          0.000942                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_misses                   15                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency        32500                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       177000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.000942                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_misses              15                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3588.938331                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2588.938331                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              20759130                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     377463000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    1464866000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.005041                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              105174                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    272289000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1359692000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.005041                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         105174                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3484.100277                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2484.100277                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 13649.402972                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                57944942                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       524925000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency      2056460000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.002593                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                150663                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    374262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   1905797000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.002593                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           150663                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3484.100277                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2484.100277                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 13649.402972                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               57944942                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      524925000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency     2056460000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.002593                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               150663                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    374262000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   1905797000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.002593                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          150663                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 146582                       # number of replacements
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4090.058697                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4089.719370                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              224414000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              500116000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   107279                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          136246937                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  2800.327765                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  1800.327765                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 12107.905937                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              136059913                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      523728500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency     2264469000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.001373                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    336704500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency   2077445000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.001373                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           136246937                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  2800.327765                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  1800.327765                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 12107.905937                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               136059913                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       523728500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency      2264469000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.001373                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    336704500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   2077445000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.001373                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          136246937                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  2800.327765                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  1800.327765                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 12107.905937                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              136059913                       # number of overall hits
-system.cpu.icache.overall_miss_latency      523728500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency     2264469000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.001373                       # miss rate for overall accesses
 system.cpu.icache.overall_misses               187024                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    336704500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   2077445000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.001373                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                 184976                       # number of replacements
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               2008.440865                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               2007.901723                       # Cycle average of tags in use
 system.cpu.icache.total_refs                136059913                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle            69827484000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.warmup_cycle           141263674000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses            337636                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2644.770157                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1643.366085                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                202957                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     356195000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency    1750760000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.398888                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses              134679                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    221326901                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1481402000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.398888                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses         134679                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses          107279                       # number of Writeback accesses(hits+misses)
@@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses             337636                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2644.770157                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1643.366085                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 12999.502521                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                 202957                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      356195000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     1750760000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.398888                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses               134679                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    221326901                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   1481402000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.398888                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses          134679                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses            444915                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2634.831752                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1643.366085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 12950.653539                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                309728                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     356195000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency    1750760000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.303849                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses              135187                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    221326901                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   1481402000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.302707                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses         134679                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                101911                       # number of replacements
 system.cpu.l2cache.sampled_refs                134679                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32141.182824                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             32127.015431                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  309728                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle           20627583000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle           41711518000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   82918                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                      98059078500                       # number of cpu cycles simulated
+system.cpu.numCycles                     198341876000                       # number of cpu cycles simulated
 system.cpu.num_insts                        136246936                       # Number of instructions executed
 system.cpu.num_refs                          58111522                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
index 08ec05c3a..c635e0e4b 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 27 2007 14:35:32
-M5 started Fri Apr 27 15:58:57 2007
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 16:44:06 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 98059078500 because target called exit()
+Exiting @ tick 198341876000 because target called exit()