diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-08-03 18:13:29 -0400 |
| commit | 62c08a75ad18fda5d06d919db6d8d31a79be9630 (patch) | |
| tree | 739253709735d1a8b5da963d2230a5418779d297 /tests/long/50.vortex/ref | |
| parent | b179c3f4cd1e89872de34d70105f703e72377029 (diff) | |
| download | gem5-62c08a75ad18fda5d06d919db6d8d31a79be9630.tar.xz | |
Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
Diffstat (limited to 'tests/long/50.vortex/ref')
12 files changed, 459 insertions, 455 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 162b46290..8de3e1042 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 2e39bfe33..6cd7ed43b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8028209 # Number of BTB hits -global.BPredUnit.BTBLookups 14249713 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35529 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 455745 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted -global.BPredUnit.lookups 16239906 # Number of BP lookups -global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target. -host_inst_rate 108698 # Simulator instruction rate (inst/s) -host_mem_usage 171788 # Number of bytes of host memory used -host_seconds 732.23 # Real time elapsed on the host -host_tick_rate 34286652 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16290741 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 8039248 # Number of BTB hits +global.BPredUnit.BTBLookups 14256738 # Number of BTB lookups +global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted +global.BPredUnit.lookups 16249458 # Number of BP lookups +global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. +host_inst_rate 176565 # Simulator instruction rate (inst/s) +host_mem_usage 212168 # Number of bytes of host memory used +host_seconds 450.78 # Real time elapsed on the host +host_tick_rate 60195419 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16328870 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.025106 # Number of seconds simulated -sim_ticks 25105678500 # Number of ticks simulated +sim_seconds 0.027135 # Number of seconds simulated +sim_ticks 27134783500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3423734 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3320893 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 48941983 +system.cpu.commit.COM:committed_per_cycle.samples 51751153 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 20096984 4106.29% - 1 10996856 2246.92% - 2 5104227 1042.91% - 3 3459002 706.76% - 4 2556441 522.34% - 5 1507300 307.98% - 6 975853 199.39% - 7 821586 167.87% - 8 3423734 699.55% + 0 22506428 4348.97% + 1 11357580 2194.65% + 2 5114502 988.29% + 3 3560855 688.07% + 4 2552506 493.23% + 5 1532718 296.17% + 6 1008932 194.96% + 7 796739 153.96% + 8 3320893 641.70% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360068 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8053439 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8296832 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.630861 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20452895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8143.771495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007108 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 145380 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses +system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20425511 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30386.313820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20275871 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4547008000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149640 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7484.182742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069117 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1010036 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010252 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.460856 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.103746 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35066272 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7567.175372 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.032949 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1155416 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 35038888 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33838927 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38426667994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1199961 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 35066272 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7567.175372 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 35038888 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32023.264084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33910856 # number of overall hits -system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.032949 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1155416 # number of overall misses -system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33838927 # number of overall hits +system.cpu.dcache.overall_miss_latency 38426667994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1199961 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988636 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200914 # number of replacements -system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200933 # number of replacements +system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use -system.cpu.dcache.total_refs 33921130 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147756 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 96488 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3648673 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101620182 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28148001 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19589576 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1262270 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284391 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 44644 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36627367 # DTB accesses +system.cpu.dcache.tagsinuse 4077.325791 # Cycle average of tags in use +system.cpu.dcache.total_refs 33851056 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 183212000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147760 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3553972 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3655574 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101758297 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28531772 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19520692 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1290098 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 144718 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36599686 # DTB accesses system.cpu.dtb.acv 39 # DTB access violations -system.cpu.dtb.hits 36456086 # DTB hits -system.cpu.dtb.misses 171281 # DTB misses -system.cpu.dtb.read_accesses 21562223 # DTB read accesses +system.cpu.dtb.hits 36425478 # DTB hits +system.cpu.dtb.misses 174208 # DTB misses +system.cpu.dtb.read_accesses 21541286 # DTB read accesses system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21405571 # DTB read hits -system.cpu.dtb.read_misses 156652 # DTB read misses -system.cpu.dtb.write_accesses 15065144 # DTB write accesses +system.cpu.dtb.read_hits 21383018 # DTB read hits +system.cpu.dtb.read_misses 158268 # DTB read misses +system.cpu.dtb.write_accesses 15058400 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15050515 # DTB write hits -system.cpu.dtb.write_misses 14629 # DTB write misses -system.cpu.fetch.Branches 16239906 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13373612 # Number of cache lines fetched -system.cpu.fetch.Cycles 33209884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 156374 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103204931 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 573221 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.323431 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13373612 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9967295 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.055410 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 15042460 # DTB write hits +system.cpu.dtb.write_misses 15940 # DTB write misses +system.cpu.fetch.Branches 16249458 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched +system.cpu.fetch.Cycles 33247227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103308047 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9981177 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 50204254 +system.cpu.fetch.rateDist.samples 53041252 system.cpu.fetch.rateDist.min_value 0 - 0 30393344 6053.94% - 1 1855009 369.49% - 2 1535971 305.94% - 3 1792342 357.01% - 4 4000264 796.80% - 5 1878750 374.22% - 6 697475 138.93% - 7 1087494 216.61% - 8 6963605 1387.05% + 0 33206262 6260.46% + 1 1871594 352.86% + 2 1529415 288.34% + 3 1809626 341.17% + 4 3985239 751.35% + 5 1867237 352.03% + 6 695846 131.19% + 7 1111736 209.60% + 8 6964297 1313.00% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13373612 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5755.491777 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 86584 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006388 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9527.365371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13297365 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 845144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88707 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2771 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 155.531172 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.737476 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13373612 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5755.491777 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency -system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006474 # miss rate for demand accesses -system.cpu.icache.demand_misses 86584 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006388 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.demand_hits 13297365 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 845144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses +system.cpu.icache.demand_misses 88707 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2771 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13373612 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5755.491777 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9527.365371 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13287028 # number of overall hits -system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006474 # miss rate for overall accesses -system.cpu.icache.overall_misses 86584 # number of overall misses -system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006388 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses +system.cpu.icache.overall_hits 13297365 # number of overall hits +system.cpu.icache.overall_miss_latency 845144000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses +system.cpu.icache.overall_misses 88707 # number of overall misses +system.cpu.icache.overall_mshr_hits 2771 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83382 # number of replacements -system.cpu.icache.sampled_refs 85430 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83888 # number of replacements +system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1922.332648 # Cycle average of tags in use -system.cpu.icache.total_refs 13287028 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 21794210000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1916.994932 # Cycle average of tags in use +system.cpu.icache.total_refs 13297365 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7104 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14739955 # Number of branches executed -system.cpu.iew.EXEC:nop 9377104 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.689247 # Inst execution rate -system.cpu.iew.EXEC:refs 36969517 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15298022 # Number of stores executed +system.cpu.idleCycles 1228316 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14745483 # Number of branches executed +system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562958 # Inst execution rate +system.cpu.iew.EXEC:refs 36941990 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291391 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42338801 # num instructions consuming a value -system.cpu.iew.WB:count 84336475 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765870 # average fanout of values written-back +system.cpu.iew.WB:consumers 42302247 # num instructions consuming a value +system.cpu.iew.WB:count 84351843 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32426009 # num instructions producing a value -system.cpu.iew.WB:rate 1.679629 # insts written-back per cycle -system.cpu.iew.WB:sent 84568976 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 400439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 20274 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22965315 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 357828 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16290741 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98799135 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21671495 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539331 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84819374 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2040 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32396966 # num instructions producing a value +system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle +system.cpu.iew.WB:sent 84585242 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 627280 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23001211 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16328870 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98972071 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21650599 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84821030 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 162 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1262270 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2540 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1290098 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 44030 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 951318 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 20550 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2585916 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1446122 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 20550 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 108250 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 292189 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.585135 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.585135 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85358705 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2621812 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1484251 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85346316 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47875288 56.09% # Type of FU issued - IntMult 42930 0.05% # Type of FU issued + IntAlu 47898540 56.12% # Type of FU issued + IntMult 42953 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 121387 0.14% # Type of FU issued - FloatCmp 87 0.00% # Type of FU issued - FloatCvt 121941 0.14% # Type of FU issued - FloatMult 50 0.00% # Type of FU issued - FloatDiv 38534 0.05% # Type of FU issued + FloatAdd 121655 0.14% # Type of FU issued + FloatCmp 88 0.00% # Type of FU issued + FloatCvt 122104 0.14% # Type of FU issued + FloatMult 53 0.00% # Type of FU issued + FloatDiv 38535 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21778158 25.51% # Type of FU issued - MemWrite 15380330 18.02% # Type of FU issued + MemRead 21753620 25.49% # Type of FU issued + MemWrite 15368768 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 989684 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 979635 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 96046 9.70% # attempts to use FU when none available + IntAlu 97095 9.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 442273 44.69% # attempts to use FU when none available - MemWrite 451365 45.61% # attempts to use FU when none available + MemRead 470602 48.04% # attempts to use FU when none available + MemWrite 411938 42.05% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 50204254 +system.cpu.iq.ISSUE:issued_per_cycle.samples 53041252 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 15297066 3046.97% - 1 13336776 2656.50% - 2 8168141 1626.98% - 3 4718425 939.85% - 4 4728752 941.90% - 5 2063960 411.11% - 6 1191217 237.27% - 7 451074 89.85% - 8 248843 49.57% + 0 17563400 3311.27% + 1 13937997 2627.77% + 2 8266118 1558.43% + 3 4784811 902.09% + 4 4627571 872.45% + 5 2066742 389.65% + 6 1112371 209.72% + 7 454506 85.69% + 8 227736 42.94% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.699988 # Inst issue rate -system.cpu.iq.iqInstsAdded 89417045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85358705 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9619776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 47402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6577473 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13398974 # ITB accesses +system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate +system.cpu.iq.iqInstsAdded 89571411 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85346316 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9777285 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49836 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6793888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13412237 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13373612 # ITB hits -system.cpu.itb.misses 25362 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5477.120197 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2477.120197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 785906500 # number of ReadExReq miss cycles +system.cpu.itb.hits 13386072 # ITB hits +system.cpu.itb.misses 26165 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143489 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 355439500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143489 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 146952 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5163.421419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2163.421419 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102374 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 230175000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.303351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 96441000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303351 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44578 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6345 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5226.319937 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2257.919622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 33161000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.558180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1383427500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6345 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14326500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6345 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147756 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147756 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.675694 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5402.763377 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102374 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1016081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.647522 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188067 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 451880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.647522 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188067 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 5865241000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5402.763377 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102374 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1016081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.647522 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188067 # number of overall misses +system.cpu.l2cache.overall_hits 102894 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188071 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 451880500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.647522 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 5865241000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 148782 # number of replacements -system.cpu.l2cache.sampled_refs 173999 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148779 # number of replacements +system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18435.407852 # Cycle average of tags in use -system.cpu.l2cache.total_refs 117570 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18483.932532 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120646 # number of writebacks -system.cpu.numCycles 50211358 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 378329 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120647 # number of writebacks +system.cpu.numCycles 54269568 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2047036 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 33543 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28456807 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 636231 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 121456625 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100818725 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60666627 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19319540 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1262270 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 711864 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8119746 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 75444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5250 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1518293 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5248 # count of temporary serializing insts renamed -system.cpu.timesIdled 2224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 64601 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28934159 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121625281 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100952073 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60736821 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19265133 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1290098 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1421425 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8189940 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2801985 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed +system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index 5992f7131..d6124e8ba 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7005 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout index f03ee0333..103f04999 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:19:28 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:08:52 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 99587aea2..8d7054aba 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=vortex lendian.raw cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 068d99b92..fcf32cd99 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 866615 # Simulator instruction rate (inst/s) -host_mem_usage 218536 # Number of bytes of host memory used -host_seconds 101.94 # Real time elapsed on the host -host_tick_rate 1271060462 # Simulator tick rate (ticks/s) +host_inst_rate 1478736 # Simulator instruction rate (inst/s) +host_mem_usage 210524 # Number of bytes of host memory used +host_seconds 59.74 # Real time elapsed on the host +host_tick_rate 2262580844 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.129569 # Number of seconds simulated -sim_ticks 129569130000 # Number of ticks simulated +sim_seconds 0.135169 # Number of seconds simulated +sim_ticks 135168711000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21389.665103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18389.665103 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1299743000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1117448000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.752992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.752992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4044374000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3594995000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5344117000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4712443000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25380.735949 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 5344117000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210558 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4712443000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.797262 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 750583000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15489.023497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12489.023497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1183919000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 954611000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1183919000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 954611000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15489.023497 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1183919000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 954611000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1876.637848 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 88438074 # ITB hits system.cpu.itb.misses 3934 # ITB misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3302294000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 995808000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22863.073210 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 142094000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4298102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4298102000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses system.cpu.l2cache.overall_misses 186874 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 147560 # number of replacements system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18265.835561 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 259138260 # number of cpu cycles simulated +system.cpu.numCycles 270337422 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index 26249ed90..598fc86c0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout index c568a72c2..82f9f1165 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:07 2008 +M5 compiled Aug 2 2008 17:07:15 +M5 started Sat Aug 2 17:10:35 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 77a49bdbd..b127e5d20 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=vortex bendian.raw cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 @@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 latency_var=0 null=false range=0:134217727 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 89c35043c..398922df0 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 809753 # Simulator instruction rate (inst/s) -host_mem_usage 216324 # Number of bytes of host memory used -host_seconds 168.12 # Real time elapsed on the host -host_tick_rate 1194295397 # Simulator tick rate (ticks/s) +host_inst_rate 1368614 # Simulator instruction rate (inst/s) +host_mem_usage 211448 # Number of bytes of host memory used +host_seconds 99.47 # Real time elapsed on the host +host_tick_rate 2062044712 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.200790 # Number of seconds simulated -sim_ticks 200790381000 # Number of ticks simulated +sim_seconds 0.205117 # Number of seconds simulated +sim_ticks 205116920000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 983722000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 847225000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2953917000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2625702000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25419.866498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3937639000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3472927000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25419.866498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 3937639000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses system.cpu.dcache.overall_misses 154904 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3472927000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.002644 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 600016000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107271 # number of writebacks system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14908.771067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2788298000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2227226000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14908.771067 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2788298000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2227226000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14908.771067 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 2788298000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2227226000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.709249 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 143009204000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2419117000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 914158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 97704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) @@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3333275000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1594175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 192777 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3333275000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses system.cpu.l2cache.overall_misses 144925 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1594175000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 120486 # number of replacements system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19341.325901 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 87413 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 401580762 # number of cpu cycles simulated +system.cpu.numCycles 410233840 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index b5ea49da4..fc5baf4b1 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 592b35b7a..dd1bc90df 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:36:59 2008 +M5 compiled Aug 2 2008 17:21:13 +M5 started Sat Aug 2 17:28:00 2008 M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424 +M5 commit date Thu Jul 31 08:01:38 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 200790381000 because target called exit() +Exiting @ tick 205116920000 because target called exit() |