diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/50.vortex/ref | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/50.vortex/ref')
13 files changed, 485 insertions, 379 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 2052b6302..dffb46ac1 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 3ea341d47..b4b0c54a3 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 7542290 # Number of BTB hits -global.BPredUnit.BTBLookups 13308941 # Number of BTB lookups -global.BPredUnit.RASInCorrect 34250 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454073 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 9847799 # Number of conditional branches predicted -global.BPredUnit.lookups 15155323 # Number of BP lookups -global.BPredUnit.usedRAS 1795531 # Number of times the RAS was used to get a target. -host_inst_rate 196409 # Simulator instruction rate (inst/s) -host_mem_usage 211144 # Number of bytes of host memory used -host_seconds 405.24 # Real time elapsed on the host -host_tick_rate 57107000 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 11563356 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 10718994 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 21578903 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 15738647 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 8001673 # Number of BTB hits +global.BPredUnit.BTBLookups 14256966 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35545 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 455902 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10551273 # Number of conditional branches predicted +global.BPredUnit.lookups 16246333 # Number of BP lookups +global.BPredUnit.usedRAS 1941036 # Number of times the RAS was used to get a target. +host_inst_rate 173213 # Simulator instruction rate (inst/s) +host_mem_usage 193376 # Number of bytes of host memory used +host_seconds 459.50 # Real time elapsed on the host +host_tick_rate 54150958 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12304370 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 10964244 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 22974359 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16298386 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.023142 # Number of seconds simulated -sim_ticks 23141799000 # Number of ticks simulated +sim_seconds 0.024882 # Number of seconds simulated +sim_ticks 24882469000 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3510282 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3430644 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 45393667 +system.cpu.commit.COM:committed_per_cycle.samples 48501675 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 16854505 3712.96% - 1 10816662 2382.86% - 2 5010201 1103.72% - 3 3353080 738.67% - 4 2515867 554.23% - 5 1511689 333.02% - 6 1009468 222.38% - 7 811913 178.86% - 8 3510282 773.30% + 0 19715966 4065.01% + 1 10943165 2256.24% + 2 5093030 1050.07% + 3 3475751 716.62% + 4 2505421 516.56% + 5 1522534 313.91% + 6 1001460 206.48% + 7 813704 167.77% + 8 3430644 707.32% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 357583 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 360143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5444219 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8051078 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.581499 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.581499 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 19849413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15478.106634 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4237.239017 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19787819 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 953358500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003103 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 61594 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 85223 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 260988500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003103 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61594 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 13805554 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30519.673214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5295.405245 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13655731 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4572549000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149823 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 807823 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 793373500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149823 # number of WriteReq MSHR misses +system.cpu.cpi 0.625230 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625230 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20377695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15251.726884 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4211.460009 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20316168 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 938393000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.003019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 61527 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 82932 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 259118500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61527 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 13807431 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 30521.435580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5307.053083 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13657610 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4572752000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010851 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149821 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 805946 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 795108000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010851 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149821 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 163.116342 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.739033 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 33654967 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26137.479484 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33443550 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5525907500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006282 # miss rate for demand accesses -system.cpu.dcache.demand_misses 211417 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 893046 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1054362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006282 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211417 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34185126 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 26076.163484 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4988.107292 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33973778 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5511145000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006182 # miss rate for demand accesses +system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 888878 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1054226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 33654967 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26137.479484 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34185126 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 26076.163484 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4988.107292 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33443550 # number of overall hits -system.cpu.dcache.overall_miss_latency 5525907500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006282 # miss rate for overall accesses -system.cpu.dcache.overall_misses 211417 # number of overall misses -system.cpu.dcache.overall_mshr_hits 893046 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1054362000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006282 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211417 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33973778 # number of overall hits +system.cpu.dcache.overall_miss_latency 5511145000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006182 # miss rate for overall accesses +system.cpu.dcache.overall_misses 211348 # number of overall misses +system.cpu.dcache.overall_mshr_hits 888878 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1054226500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,92 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200972 # number of replacements -system.cpu.dcache.sampled_refs 205068 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200926 # number of replacements +system.cpu.dcache.sampled_refs 205022 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.963353 # Cycle average of tags in use -system.cpu.dcache.total_refs 33449942 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 119008000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4080.923075 # Cycle average of tags in use +system.cpu.dcache.total_refs 33980148 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 120631000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147761 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 971695 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 97371 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3417858 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 96162354 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 25952342 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 18439987 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 888885 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 288762 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 29644 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 15155323 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 12535185 # Number of cache lines fetched -system.cpu.fetch.Cycles 31179449 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 131701 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 97686537 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 470452 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.327452 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 12535185 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9337821 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.110656 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 953936 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 96699 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3650405 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101647473 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 27934130 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19589260 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1261472 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284553 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 24350 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36627778 # DTB accesses +system.cpu.dtb.acv 37 # DTB access violations +system.cpu.dtb.hits 36455125 # DTB hits +system.cpu.dtb.misses 172653 # DTB misses +system.cpu.dtb.read_accesses 21565019 # DTB read accesses +system.cpu.dtb.read_acv 35 # DTB read access violations +system.cpu.dtb.read_hits 21407076 # DTB read hits +system.cpu.dtb.read_misses 157943 # DTB read misses +system.cpu.dtb.write_accesses 15062759 # DTB write accesses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_hits 15048049 # DTB write hits +system.cpu.dtb.write_misses 14710 # DTB write misses +system.cpu.fetch.Branches 16246333 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13375683 # Number of cache lines fetched +system.cpu.fetch.Cycles 33194597 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 152184 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103251284 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 572846 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.326473 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13375683 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9942709 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.074854 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 46282553 +system.cpu.fetch.rateDist.samples 49763148 system.cpu.fetch.rateDist.min_value 0 - 0 27638291 5971.64% - 1 1733920 374.64% - 2 1408099 304.24% - 3 1707036 368.83% - 4 3689148 797.09% - 5 1739866 375.92% - 6 655334 141.59% - 7 1059487 228.92% - 8 6651372 1437.12% + 0 29969634 6022.46% + 1 1857821 373.33% + 2 1524433 306.34% + 3 1786134 358.93% + 4 3977224 799.23% + 5 1866445 375.07% + 6 698149 140.29% + 7 1110284 223.11% + 8 6973024 1401.24% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 12534294 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4593.252212 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2552.911039 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12448414 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 394468500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006852 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 85880 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 891 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 219244000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006852 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85880 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13374854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4582.447586 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2544.287368 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13289333 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 391895500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006394 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 85521 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 829 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 217590000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006394 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85521 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 144.958009 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 155.392629 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 12534294 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4593.252212 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency -system.cpu.icache.demand_hits 12448414 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 394468500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006852 # miss rate for demand accesses -system.cpu.icache.demand_misses 85880 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 891 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 219244000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006852 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85880 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13374854 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4582.447586 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2544.287368 # average overall mshr miss latency +system.cpu.icache.demand_hits 13289333 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 391895500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006394 # miss rate for demand accesses +system.cpu.icache.demand_misses 85521 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 829 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 217590000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006394 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85521 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 12534294 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4593.252212 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13374854 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4582.447586 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2544.287368 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12448414 # number of overall hits -system.cpu.icache.overall_miss_latency 394468500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006852 # miss rate for overall accesses -system.cpu.icache.overall_misses 85880 # number of overall misses -system.cpu.icache.overall_mshr_hits 891 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 219244000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006852 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85880 # number of overall MSHR misses +system.cpu.icache.overall_hits 13289333 # number of overall hits +system.cpu.icache.overall_miss_latency 391895500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006394 # miss rate for overall accesses +system.cpu.icache.overall_misses 85521 # number of overall misses +system.cpu.icache.overall_mshr_hits 829 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 217590000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006394 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85521 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -217,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83828 # number of replacements -system.cpu.icache.sampled_refs 85876 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83473 # number of replacements +system.cpu.icache.sampled_refs 85521 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1919.939531 # Cycle average of tags in use -system.cpu.icache.total_refs 12448414 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 20180672000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1922.769682 # Cycle average of tags in use +system.cpu.icache.total_refs 13289333 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 21643859000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 779486 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14215317 # Number of branches executed -system.cpu.iew.EXEC:nop 9054056 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.776804 # Inst execution rate -system.cpu.iew.EXEC:refs 36085022 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15098216 # Number of stores executed +system.cpu.idleCycles 1231826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14739683 # Number of branches executed +system.cpu.iew.EXEC:nop 9380523 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.704450 # Inst execution rate +system.cpu.iew.EXEC:refs 36969776 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15295559 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 41423091 # num instructions consuming a value -system.cpu.iew.WB:count 81970056 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.763712 # average fanout of values written-back +system.cpu.iew.WB:consumers 42405904 # num instructions consuming a value +system.cpu.iew.WB:count 84333016 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765386 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 31635305 # num instructions producing a value -system.cpu.iew.WB:rate 1.771079 # insts written-back per cycle -system.cpu.iew.WB:sent 82027383 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 388269 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 17461 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 21578903 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4692 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 341214 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 15738647 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 93782111 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 20986806 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 455724 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 82235016 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2252 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32456867 # num instructions producing a value +system.cpu.iew.WB:rate 1.694688 # insts written-back per cycle +system.cpu.iew.WB:sent 84566644 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 400717 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 20492 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 22974359 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4987 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 359590 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16298386 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98827714 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21674217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 545926 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84818805 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2571 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 122 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 888885 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 3197 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1261472 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3172 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 937737 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 950 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 945093 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1085 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 19015 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1226 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1199504 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 894028 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 19015 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 105591 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 282678 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.719692 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.719692 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 82690740 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19531 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1312 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2594960 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1453767 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19531 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 108348 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 292369 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.599412 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599412 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85364731 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 46107608 55.76% # Type of FU issued - IntMult 43061 0.05% # Type of FU issued + IntAlu 47879047 56.09% # Type of FU issued + IntMult 43747 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 119602 0.14% # Type of FU issued - FloatCmp 87 0.00% # Type of FU issued - FloatCvt 120853 0.15% # Type of FU issued + FloatAdd 121378 0.14% # Type of FU issued + FloatCmp 86 0.00% # Type of FU issued + FloatCvt 121979 0.14% # Type of FU issued FloatMult 50 0.00% # Type of FU issued - FloatDiv 37774 0.05% # Type of FU issued + FloatDiv 38527 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21079728 25.49% # Type of FU issued - MemWrite 15181977 18.36% # Type of FU issued + MemRead 21782176 25.52% # Type of FU issued + MemWrite 15377741 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 974009 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 969096 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011352 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 90058 9.25% # attempts to use FU when none available + IntAlu 95806 9.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -299,62 +311,66 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 437339 44.90% # attempts to use FU when none available - MemWrite 446612 45.85% # attempts to use FU when none available + MemRead 442018 45.61% # attempts to use FU when none available + MemWrite 431272 44.50% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 46282553 +system.cpu.iq.ISSUE:issued_per_cycle.samples 49763148 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 12550048 2711.62% - 1 12875827 2782.00% - 2 7785024 1682.06% - 3 4673558 1009.79% - 4 4500672 972.43% - 5 2074677 448.26% - 6 1137561 245.79% - 7 458736 99.12% - 8 226450 48.93% + 0 14890253 2992.22% + 1 13307982 2674.26% + 2 8090593 1625.82% + 3 4789845 962.53% + 4 4747984 954.12% + 5 2061711 414.30% + 6 1164817 234.07% + 7 463069 93.05% + 8 246894 49.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.786650 # Inst issue rate -system.cpu.iq.iqInstsAdded 84723363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 82690740 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4692 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4940751 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53730 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3594449 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 143476 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4086.446514 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2086.446514 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 586307000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 1.715421 # Inst issue rate +system.cpu.iq.iqInstsAdded 89442204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85364731 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4987 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9646731 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49535 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 404 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6611614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13401083 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 13375683 # ITB hits +system.cpu.itb.misses 25400 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4092.480574 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2092.480574 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 587250500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143476 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 299355000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143495 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 300260500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143476 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4144.894478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2144.894478 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 98804 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 201703000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.329992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 48663 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.329992 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 48663 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6368 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4226.366206 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2231.626884 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 26913500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143495 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147048 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4140.515824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2140.515824 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 98388 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 201477500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.330912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 48660 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 104157500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.330912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 48660 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4240.542245 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.591425 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 26902000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6368 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14211000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14227000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6368 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses @@ -362,38 +378,38 @@ system.cpu.l2cache.Writeback_mshr_miss_rate 1 # system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.459748 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.449354 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290943 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4101.249616 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 98804 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 788010000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.660401 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 192139 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290543 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4104.644688 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2104.644688 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 98388 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 788728000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.661365 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 192155 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 403732000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.660401 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 192139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 404418000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.661365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 192155 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290943 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4101.249616 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290543 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4104.644688 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2104.644688 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 98804 # number of overall hits -system.cpu.l2cache.overall_miss_latency 788010000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.660401 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 192139 # number of overall misses +system.cpu.l2cache.overall_hits 98388 # number of overall hits +system.cpu.l2cache.overall_miss_latency 788728000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.661365 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 192155 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 403732000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.660401 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 192139 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 404418000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.661365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 192155 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -405,31 +421,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 25941 # number of replacements +system.cpu.l2cache.replacements 25943 # number of replacements system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 4585.524484 # Cycle average of tags in use -system.cpu.l2cache.total_refs 102938 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 4581.530519 # Cycle average of tags in use +system.cpu.l2cache.total_refs 102503 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 46282553 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 249890 # Number of cycles rename is blocking +system.cpu.numCycles 49763148 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 263435 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 36341 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 26244762 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 565515 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 115161809 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 95469817 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 57208765 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 18176186 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 888885 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 649163 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4661884 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 73667 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4695 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1420326 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4693 # count of temporary serializing insts renamed -system.cpu.timesIdled 518 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 34724 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28245765 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 545942 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 121486902 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100840274 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60680951 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19296581 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1261472 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 621968 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8134070 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 73927 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5255 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1395173 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5253 # count of temporary serializing insts renamed +system.cpu.timesIdled 678 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 5339d79af..4745ee94c 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 16fb6367e..f06392b4f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 840697 # Simulator instruction rate (inst/s) -host_mem_usage 152968 # Number of bytes of host memory used -host_seconds 105.08 # Real time elapsed on the host -host_tick_rate 420346781 # Simulator tick rate (ticks/s) +host_inst_rate 2496642 # Simulator instruction rate (inst/s) +host_mem_usage 184388 # Number of bytes of host memory used +host_seconds 35.38 # Real time elapsed on the host +host_tick_rate 1249741953 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.044170 # Number of seconds simulated -sim_ticks 44170336500 # Number of ticks simulated +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.044221 # Number of seconds simulated +sim_ticks 44221003000 # Number of ticks simulated +system.cpu.dtb.accesses 34987415 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 34890015 # DTB hits +system.cpu.dtb.misses 97400 # DTB misses +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 88442007 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 88438073 # ITB hits +system.cpu.itb.misses 3934 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 88340674 # number of cpu cycles simulated -system.cpu.num_insts 88340674 # Number of instructions executed -system.cpu.num_refs 35224019 # Number of memory references +system.cpu.numCycles 88442007 # number of cpu cycles simulated +system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg index 327142d7c..472b08431 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg @@ -134,7 +134,7 @@ DB Handle Chunk's StackPtr = 20797 DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 40054800 + KERNEL in CORE[ 1] Restored @ 4005c800 OPEN File ./input/lendian.wnv *Status = 0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 878ba709b..99534f902 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index b10e7249f..42618bd93 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1495977 # Simulator instruction rate (inst/s) -host_mem_usage 209700 # Number of bytes of host memory used -host_seconds 59.05 # Real time elapsed on the host -host_tick_rate 2185213288 # Simulator tick rate (ticks/s) +host_inst_rate 1453070 # Simulator instruction rate (inst/s) +host_mem_usage 191752 # Number of bytes of host memory used +host_seconds 60.80 # Real time elapsed on the host +host_tick_rate 2124138006 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.129042 # Number of seconds simulated -sim_ticks 129042205000 # Number of ticks simulated +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.129140 # Number of seconds simulated +sim_ticks 129139604000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency @@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.920336 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4080.930479 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 737102000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 737173000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks -system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 34987415 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 34890015 # DTB hits +system.cpu.dtb.misses 97400 # DTB misses +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency -system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits +system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 88264239 # number of overall hits +system.cpu.icache.overall_hits 88361638 # number of overall hits system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1876.903920 # Cycle average of tags in use -system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1876.941758 # Cycle average of tags in use +system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 88442008 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 88438074 # ITB hits +system.cpu.itb.misses 3934 # ITB misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 24953 # number of replacements system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 4393.051484 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 4393.054480 # Cycle average of tags in use system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 129042205000 # number of cpu cycles simulated -system.cpu.num_insts 88340674 # Number of instructions executed -system.cpu.num_refs 35224019 # Number of memory references +system.cpu.numCycles 129139604000 # number of cpu cycles simulated +system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index da377104f..dcd40ebc7 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index 9dd2e7465..c76c08dcd 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 672762 # Simulator instruction rate (inst/s) -host_mem_usage 151516 # Number of bytes of host memory used -host_seconds 202.52 # Real time elapsed on the host -host_tick_rate 336380340 # Simulator tick rate (ticks/s) +host_inst_rate 1682182 # Simulator instruction rate (inst/s) +host_mem_usage 185356 # Number of bytes of host memory used +host_seconds 80.93 # Real time elapsed on the host +host_tick_rate 842064489 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.068123 # Number of seconds simulated -sim_ticks 68123467500 # Number of ticks simulated +sim_insts 136141055 # Number of instructions simulated +sim_seconds 0.068150 # Number of seconds simulated +sim_ticks 68149604500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 136246936 # number of cpu cycles simulated -system.cpu.num_insts 136246936 # Number of instructions executed -system.cpu.num_refs 58111522 # Number of memory references +system.cpu.numCycles 136299210 # number of cpu cycles simulated +system.cpu.num_insts 136141055 # Number of instructions executed +system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 13addb638..6a817bd73 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 16:40:43 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 23:33:10 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 68123467500 because target called exit() +Exiting @ tick 68149604500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 5f9deac8a..1069d2547 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index e924e185b..2bb84bd57 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1128502 # Simulator instruction rate (inst/s) -host_mem_usage 210664 # Number of bytes of host memory used -host_seconds 120.73 # Real time elapsed on the host -host_tick_rate 1658768570 # Simulator tick rate (ticks/s) +host_inst_rate 960220 # Simulator instruction rate (inst/s) +host_mem_usage 192724 # Number of bytes of host memory used +host_seconds 141.78 # Real time elapsed on the host +host_tick_rate 1412855280 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.200268 # Number of seconds simulated -sim_ticks 200267857000 # Number of ticks simulated +sim_insts 136141055 # Number of instructions simulated +sim_seconds 0.200317 # Number of seconds simulated +sim_ticks 200316584000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency @@ -86,53 +86,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.106244 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.107113 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 584597000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 584680000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks -system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 136295664 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 136108640 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.499749 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 727.760287 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 136295664 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency -system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits +system.cpu.icache.demand_hits 136108640 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 136295664 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136059913 # number of overall hits +system.cpu.icache.overall_hits 136108640 # number of overall hits system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -148,9 +148,9 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.859894 # Cycle average of tags in use -system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 142624255000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 2006.864278 # Cycle average of tags in use +system.cpu.icache.total_refs 136108640 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 142656863000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 22010 # number of replacements system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6146.860431 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6146.948797 # Cycle average of tags in use system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 200267857000 # number of cpu cycles simulated -system.cpu.num_insts 136246936 # Number of instructions executed -system.cpu.num_refs 58111522 # Number of memory references +system.cpu.numCycles 200316584000 # number of cpu cycles simulated +system.cpu.num_insts 136141055 # Number of instructions executed +system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 862e98203..e6db66f3d 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 12:23:15 -M5 started Sun Aug 12 16:52:13 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 23:34:32 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 200267857000 because target called exit() +Exiting @ tick 200316584000 because target called exit() |