diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/50.vortex/ref | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/50.vortex/ref')
25 files changed, 471 insertions, 465 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 46d47f481..2452e8b3b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 55fcb321a..124e9408d 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 15:40:30 -M5 revision Unknown -M5 started Feb 18 2011 18:53:22 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 883ec05af..e986b9b66 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 140237 # Simulator instruction rate (inst/s) -host_mem_usage 237028 # Number of bytes of host memory used -host_seconds 629.94 # Real time elapsed on the host -host_tick_rate 69352666 # Simulator tick rate (ticks/s) +host_inst_rate 198512 # Simulator instruction rate (inst/s) +host_mem_usage 241900 # Number of bytes of host memory used +host_seconds 445.02 # Real time elapsed on the host +host_tick_rate 98171525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.043688 # Number of seconds simulated sim_ticks 43687852500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 35033051 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 40.125186 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4678520 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 11659809 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 753993 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 9173160 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 14237671 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 44841137 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 753993 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 13000484 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 550902 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 93058128 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic system.cpu.activity 70.715162 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 35033051 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 40.125186 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 4678520 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 11659809 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 753993 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 9173160 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 14237671 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed system.cpu.comInts 30791227 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 204344 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994103 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4071.844772 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994103 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 48047.843576 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.execution_unit.executions 44841137 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 753993 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 13000484 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 550902 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 11384439 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 18620.927639 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 88669 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.918759 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1881.619179 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.918759 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 11384439 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18620.927639 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency @@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 174462 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.093044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.476016 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3048.873160 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15598.097053 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.093044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.476016 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 293012 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52103.234515 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency @@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 18646.970214 # Cy system.cpu.l2cache.total_refs 134496 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120516 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 41101 # Number of Multipy Operations Executed system.cpu.numCycles 87375706 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 93058128 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 52546881 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 61787872 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 42493951 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 44881755 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 48181868 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 39193838 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 46079607 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 41296099 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63477269 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 23898437 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 39338499 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 48037207 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 42493951 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 44881755 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 48181868 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 39193838 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46079607 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 41296099 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63477269 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 23898437 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39338499 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 48037207 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 69007682 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 289197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 22a45b8cb..c10dc5f2b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 78849816e..0e04160b4 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:45:41 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:35 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 2c566c667..2aed2a2e0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229170 # Simulator instruction rate (inst/s) -host_mem_usage 217968 # Number of bytes of host memory used -host_seconds 347.30 # Real time elapsed on the host -host_tick_rate 73616120 # Simulator tick rate (ticks/s) +host_inst_rate 329538 # Simulator instruction rate (inst/s) +host_mem_usage 213968 # Number of bytes of host memory used +host_seconds 241.53 # Real time elapsed on the host +host_tick_rate 105857368 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.025567 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 450273 # Nu system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3841167 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 49654357 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.779112 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 49654357 # Number of insts commited each cycle -system.cpu.commit.COM:count 88340672 # Number of instructions committed -system.cpu.commit.COM:fp_insts 267754 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1661057 # Number of function calls committed. -system.cpu.commit.COM:int_insts 77942044 # Number of committed integer instructions. -system.cpu.commit.COM:loads 20276638 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 34890015 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted +system.cpu.commit.branches 13754477 # Number of branches committed +system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle +system.cpu.commit.count 88340672 # Number of instructions committed +system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1661057 # Number of function calls committed. +system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. +system.cpu.commit.loads 20276638 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 34890015 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction @@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 205151 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995275 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency @@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4076.644885 # Cy system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 161514 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2460997 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 97681 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3594435 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 100084760 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 27762644 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19396266 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1063649 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 276834 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 34450 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle +system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 36973918 # DTB accesses system.cpu.dtb.data_acv 20 # DTB access violations system.cpu.dtb.data_hits 36772232 # DTB hits @@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 85058 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.935566 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency @@ -233,21 +233,13 @@ system.cpu.icache.total_refs 13070837 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14700654 # Number of branches executed -system.cpu.iew.EXEC:nop 9311504 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.660486 # Inst execution rate -system.cpu.iew.EXEC:refs 36975872 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15225695 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 40429267 # num instructions consuming a value -system.cpu.iew.WB:count 84366668 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.767758 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 31039892 # num instructions producing a value -system.cpu.iew.WB:rate 1.649898 # insts written-back per cycle -system.cpu.iew.WB:sent 84634554 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 14700654 # Number of branches executed +system.cpu.iew.exec_nop 9311504 # number of nop insts executed +system.cpu.iew.exec_rate 1.660486 # Inst execution rate +system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed +system.cpu.iew.exec_stores 15225695 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions @@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1168217 # system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value +system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 31039892 # num instructions producing a value +system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle +system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 112360564 # number of integer regfile reads system.cpu.int_regfile_writes 55786710 # number of integer regfile writes system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 85477986 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1052413 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 50718006 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.685358 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 50718006 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.671631 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses @@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 8137764 # Nu system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle +system.cpu.iq.rate 1.671631 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 175063 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.091039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.482420 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency @@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 51134470 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 1389160 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 11049 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28153155 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 39 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 119490611 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 99297358 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 59691366 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19024050 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1063649 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1018413 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7144485 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 428893 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 119061718 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 69579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5023 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2212492 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5020 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed +system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 139404893 # The number of ROB reads system.cpu.rob.rob_writes 190882895 # The number of ROB writes system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout index 47e63ab68..01b718e71 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 1ad0b8bf6..cf38a10a9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1614429 # Simulator instruction rate (inst/s) -host_mem_usage 226740 # Number of bytes of host memory used -host_seconds 54.72 # Real time elapsed on the host -host_tick_rate 808136192 # Simulator tick rate (ticks/s) +host_inst_rate 5661046 # Simulator instruction rate (inst/s) +host_mem_usage 204384 # Number of bytes of host memory used +host_seconds 15.61 # Real time elapsed on the host +host_tick_rate 2833734985 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 52319251 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_mem_refs 34987415 # number of memory refs system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 6f171a7fa..7e8e19e97 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index 4f3f97870..c65ed7989 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:02:47 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 4a3fdb24c..d459892f5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 599191 # Simulator instruction rate (inst/s) -host_mem_usage 234452 # Number of bytes of host memory used -host_seconds 147.43 # Real time elapsed on the host -host_tick_rate 910763031 # Simulator tick rate (ticks/s) +host_inst_rate 2375162 # Simulator instruction rate (inst/s) +host_mem_usage 212132 # Number of bytes of host memory used +host_seconds 37.19 # Real time elapsed on the host +host_tick_rate 3610204318 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.134277 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 204344 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995815 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 76436 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.913772 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 173780 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.085649 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.482430 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 52319251 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_mem_refs 34987415 # number of memory refs system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls +system.cpu.workload.num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 6767fc19c..2426ff257 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 3d6783bda..8381f7581 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:24:14 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:18:26 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 2c7e07f74..50e06cc2a 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 216149 # Simulator instruction rate (inst/s) -host_mem_usage 267340 # Number of bytes of host memory used -host_seconds 465.57 # Real time elapsed on the host -host_tick_rate 85683012 # Simulator tick rate (ticks/s) +host_inst_rate 252526 # Simulator instruction rate (inst/s) +host_mem_usage 223792 # Number of bytes of host memory used +host_seconds 398.51 # Real time elapsed on the host +host_tick_rate 100102950 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100633305 # Number of instructions simulated sim_seconds 0.039892 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 830445 # Nu system.cpu.BPredUnit.condPredicted 11914381 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 18227498 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1851553 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 13669912 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2877364 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 76617428 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.313524 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 76617428 # Number of insts commited each cycle -system.cpu.commit.COM:count 100638857 # Number of instructions committed -system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 1679850 # Number of function calls committed. -system.cpu.commit.COM:int_insts 91477923 # Number of committed integer instructions. -system.cpu.commit.COM:loads 27308393 # Number of loads committed -system.cpu.commit.COM:membars 15920 # Number of memory barriers committed -system.cpu.commit.COM:refs 47865415 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 800437 # The number of times a branch was mispredicted +system.cpu.commit.branches 13669912 # Number of branches committed +system.cpu.commit.bw_lim_events 2877364 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 100638857 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 700914 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 13588852 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 76617428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.313524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 76617428 # Number of insts commited each cycle +system.cpu.commit.count 100638857 # Number of instructions committed +system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1679850 # Number of function calls committed. +system.cpu.commit.int_insts 91477923 # Number of committed integer instructions. +system.cpu.commit.loads 27308393 # Number of loads committed +system.cpu.commit.membars 15920 # Number of memory barriers committed +system.cpu.commit.refs 47865415 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 100633305 # Number of Instructions Simulated system.cpu.committedInsts_total 100633305 # Number of Instructions Simulated system.cpu.cpi 0.792814 # CPI: Cycles Per Instruction @@ -109,8 +109,8 @@ system.cpu.dcache.demand_mshr_misses 161560 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994984 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4075.453819 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994984 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 46799358 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 31971.352710 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency @@ -132,15 +132,15 @@ system.cpu.dcache.tagsinuse 4075.453819 # Cy system.cpu.dcache.total_refs 45185537 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 327416000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 123381 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 28767889 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93628 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3727749 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 120621461 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 25476849 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 21756774 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2130394 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 323992 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 615915 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 28767889 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 93628 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3727749 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 120621461 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 25476849 # Number of cycles decode is idle +system.cpu.decode.RunCycles 21756774 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2130394 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 323992 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 615915 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -225,8 +225,8 @@ system.cpu.icache.demand_mshr_misses 24591 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.875696 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1793.424749 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.875696 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 11770565 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 12757.129371 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency @@ -249,21 +249,13 @@ system.cpu.icache.total_refs 11745142 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 1035652 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14732348 # Number of branches executed -system.cpu.iew.EXEC:nop 77233 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.323750 # Inst execution rate -system.cpu.iew.EXEC:refs 49299625 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 21011299 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 107738460 # num instructions consuming a value -system.cpu.iew.WB:count 105037825 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.490563 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 52852456 # num instructions producing a value -system.cpu.iew.WB:rate 1.316536 # insts written-back per cycle -system.cpu.iew.WB:sent 105209239 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 874742 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 14732348 # Number of branches executed +system.cpu.iew.exec_nop 77233 # number of nop insts executed +system.cpu.iew.exec_rate 1.323750 # Inst execution rate +system.cpu.iew.exec_refs 49299625 # number of memory reference insts executed +system.cpu.iew.exec_stores 21011299 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 976865 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 29744817 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 738677 # Number of dispatched non-speculative instructions @@ -291,103 +283,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1650781 # system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 107738460 # num instructions consuming a value +system.cpu.iew.wb_count 105037825 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.490563 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 52852456 # num instructions producing a value +system.cpu.iew.wb_rate 1.316536 # insts written-back per cycle +system.cpu.iew.wb_sent 105209239 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 252839831 # number of integer regfile reads system.cpu.int_regfile_writes 78127703 # number of integer regfile writes system.cpu.ipc 1.261330 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.261330 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 106544489 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1792992 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 78747821 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.352983 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 78747821 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.335421 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 106544489 # Type of FU issued system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 160 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 144 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1792992 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 108337399 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 293735316 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 105037757 # Number of integer instruction queue wakeup accesses @@ -399,6 +381,24 @@ system.cpu.iq.iqSquashedInstsExamined 13400232 # Nu system.cpu.iq.iqSquashedInstsIssued 105692 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 54866 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 21923544 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 78747821 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.352983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 78747821 # Number of insts issued each cycle +system.cpu.iq.rate 1.335421 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -473,10 +473,10 @@ system.cpu.l2cache.demand_mshr_misses 134835 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070082 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.488463 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2296.436358 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16005.968558 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.488463 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 186127 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34374.638605 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency @@ -507,28 +507,28 @@ system.cpu.misc_regfile_writes 34408 # nu system.cpu.numCycles 79783473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2921057 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 75878617 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 205954 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 27124909 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 315599119 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 118180992 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 90551096 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 20607135 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2130394 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4279204 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14672443 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 83429 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 315515690 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 759000 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12013897 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 759711 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 2921057 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 75878617 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 205954 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 27124909 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 315599119 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 118180992 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 90551096 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 20607135 # Number of cycles rename is running +system.cpu.rename.SquashCycles 2130394 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 4279204 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 14672443 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 83429 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 315515690 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 759000 # count of serializing insts renamed +system.cpu.rename.skidInsts 12013897 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 759711 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 187942474 # The number of ROB reads system.cpu.rob.rob_writes 230588533 # The number of ROB writes system.cpu.timesIdled 60808 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini index 262e03017..d284ed163 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -61,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout index 66dafc4ae..6efadf55b 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:44:05 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:19:31 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt index c99f59463..a40e03286 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1067183 # Simulator instruction rate (inst/s) -host_mem_usage 254708 # Number of bytes of host memory used -host_seconds 94.30 # Real time elapsed on the host -host_tick_rate 571936208 # Simulator tick rate (ticks/s) +host_inst_rate 3930429 # Simulator instruction rate (inst/s) +host_mem_usage 213832 # Number of bytes of host memory used +host_seconds 25.60 # Real time elapsed on the host +host_tick_rate 2106429498 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100632437 # Number of instructions simulated sim_seconds 0.053932 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 73126599 # nu system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini index c681e2402..8d849c15a 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -164,12 +164,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout index b08e3aaf1..7b793d7b7 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 18:45:50 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 13:20:07 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 0bdccd82b..4142f5d9a 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 558313 # Simulator instruction rate (inst/s) -host_mem_usage 262448 # Number of bytes of host memory used -host_seconds 178.74 # Real time elapsed on the host -host_tick_rate 744762819 # Simulator tick rate (ticks/s) +host_inst_rate 2031292 # Simulator instruction rate (inst/s) +host_mem_usage 221580 # Number of bytes of host memory used +host_seconds 49.13 # Real time elapsed on the host +host_tick_rate 2709639216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 99791663 # Number of instructions simulated sim_seconds 0.133117 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 159998 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995345 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 18908 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.847746 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 133917 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.066099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.489066 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 73126599 # nu system.cpu.num_load_insts 27307109 # Number of load instructions system.cpu.num_mem_refs 47862848 # number of memory refs system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index 7f5789393..8359194cf 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:11 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:19:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index d6bfda298..25cfa073d 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1204089 # Simulator instruction rate (inst/s) -host_mem_usage 228576 # Number of bytes of host memory used -host_seconds 113.06 # Real time elapsed on the host -host_tick_rate 602742669 # Simulator tick rate (ticks/s) +host_inst_rate 4754404 # Simulator instruction rate (inst/s) +host_mem_usage 206464 # Number of bytes of host memory used +host_seconds 28.63 # Real time elapsed on the host +host_tick_rate 2379947985 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 113225733 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_mem_refs 58160249 # number of memory refs system.cpu.num_store_insts 20884381 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 8ec9f75ef..4d41b9cb9 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index b27952d03..0a7053375 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:39 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:21:09 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index eb6eca0bd..f75c53329 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 463084 # Simulator instruction rate (inst/s) -host_mem_usage 236284 # Number of bytes of host memory used -host_seconds 293.98 # Real time elapsed on the host -host_tick_rate 690315679 # Simulator tick rate (ticks/s) +host_inst_rate 2437881 # Simulator instruction rate (inst/s) +host_mem_usage 214216 # Number of bytes of host memory used +host_seconds 55.84 # Real time elapsed on the host +host_tick_rate 3634125508 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.202942 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 150663 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997953 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4087.617150 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997953 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 49432.508313 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 187024 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.978868 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.978868 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency @@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 140161 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.121030 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.481204 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 3965.924560 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15768.107062 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.121030 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.481204 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 113225732 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_mem_refs 58160249 # number of memory refs system.cpu.num_store_insts 20884381 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls +system.cpu.workload.num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- |