diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-12 19:43:55 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-12 19:43:55 -0400 |
| commit | d114e5fae6ffb83a1145208532def7654cc9dd75 (patch) | |
| tree | d54b53635428baefbb0ef25715e1059a2bad1185 /tests/long/50.vortex/ref | |
| parent | 02353a60ee6ce831302067aae38bc31b739f14e5 (diff) | |
| download | gem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz | |
Regression: Update stats for cache changes.
--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/long/50.vortex/ref')
8 files changed, 615 insertions, 558 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 8c32bfa79..2052b6302 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload +children=dcache fuPool icache l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -21,6 +21,7 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +cachePorts=200 choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -74,8 +75,18 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 squashWidth=8 system=system +tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 @@ -85,21 +96,21 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -107,12 +118,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -128,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu.fuPool.FUList0] type=FUDesc -children=opList0 +children=opList count=6 -opList=system.cpu.fuPool.FUList0.opList0 +opList=system.cpu.fuPool.FUList0.opList -[system.cpu.fuPool.FUList0.opList0] +[system.cpu.fuPool.FUList0.opList] type=OpDesc issueLat=1 opClass=IntAlu @@ -206,11 +215,11 @@ opLat=24 [system.cpu.fuPool.FUList4] type=FUDesc -children=opList0 +children=opList count=0 -opList=system.cpu.fuPool.FUList4.opList0 +opList=system.cpu.fuPool.FUList4.opList -[system.cpu.fuPool.FUList4.opList0] +[system.cpu.fuPool.FUList4.opList] type=OpDesc issueLat=1 opClass=MemRead @@ -218,11 +227,11 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc -children=opList0 +children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList0 +opList=system.cpu.fuPool.FUList5.opList -[system.cpu.fuPool.FUList5.opList0] +[system.cpu.fuPool.FUList5.opList] type=OpDesc issueLat=1 opClass=MemWrite @@ -248,11 +257,11 @@ opLat=1 [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 +children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList0 +opList=system.cpu.fuPool.FUList7.opList -[system.cpu.fuPool.FUList7.opList0] +[system.cpu.fuPool.FUList7.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -260,21 +269,21 @@ opLat=3 [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -282,12 +291,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -298,21 +305,21 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -320,12 +327,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -343,6 +348,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw @@ -366,7 +374,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index bf6f402cd..3ea341d47 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 7411086 # Number of BTB hits -global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups -global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted -global.BPredUnit.lookups 14988034 # Number of BP lookups -global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target. -host_inst_rate 99683 # Simulator instruction rate (inst/s) -host_mem_usage 159476 # Number of bytes of host memory used -host_seconds 798.45 # Real time elapsed on the host -host_tick_rate 35303213 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7542290 # Number of BTB hits +global.BPredUnit.BTBLookups 13308941 # Number of BTB lookups +global.BPredUnit.RASInCorrect 34250 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 454073 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 9847799 # Number of conditional branches predicted +global.BPredUnit.lookups 15155323 # Number of BP lookups +global.BPredUnit.usedRAS 1795531 # Number of times the RAS was used to get a target. +host_inst_rate 196409 # Simulator instruction rate (inst/s) +host_mem_usage 211144 # Number of bytes of host memory used +host_seconds 405.24 # Real time elapsed on the host +host_tick_rate 57107000 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 11563356 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 10718994 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21578903 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15738647 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.028188 # Number of seconds simulated -sim_ticks 28187684500 # Number of ticks simulated +sim_seconds 0.023142 # Number of seconds simulated +sim_ticks 23141799000 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3510282 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 55590975 +system.cpu.commit.COM:committed_per_cycle.samples 45393667 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 26501535 4767.24% - 1 10970497 1973.43% - 2 5466463 983.34% - 3 3506601 630.79% - 4 2372940 426.86% - 5 1558557 280.36% - 6 1098347 197.58% - 7 885461 159.28% - 8 3230574 581.13% + 0 16854505 3712.96% + 1 10816662 2382.86% + 2 5010201 1103.72% + 3 3353080 738.67% + 4 2515867 554.23% + 5 1511689 333.02% + 6 1009468 222.38% + 7 811913 178.86% + 8 3510282 773.30% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 357583 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5444219 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses +system.cpu.cpi 0.581499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.581499 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 19849413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15478.106634 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4237.239017 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19787819 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 953358500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.003103 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 61594 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 85223 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 260988500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003103 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61594 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 13805554 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 30519.673214 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5295.405245 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13655731 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4572549000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149823 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 807823 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 793373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149823 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 163.116342 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses -system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 33654967 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 26137.479484 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33443550 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5525907500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006282 # miss rate for demand accesses +system.cpu.dcache.demand_misses 211417 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 893046 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1054362000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006282 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211417 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 33654967 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 26137.479484 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33960866 # number of overall hits -system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses -system.cpu.dcache.overall_misses 702345 # number of overall misses -system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33443550 # number of overall hits +system.cpu.dcache.overall_miss_latency 5525907500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006282 # miss rate for overall accesses +system.cpu.dcache.overall_misses 211417 # number of overall misses +system.cpu.dcache.overall_mshr_hits 893046 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1054362000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006282 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211417 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +120,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200859 # number of replacements -system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200972 # number of replacements +system.cpu.dcache.sampled_refs 205068 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use -system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147753 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched -system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4079.963353 # Cycle average of tags in use +system.cpu.dcache.total_refs 33449942 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 119008000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147761 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 971695 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97371 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3417858 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 96162354 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 25952342 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 18439987 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 888885 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 288762 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 29644 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 15155323 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12535185 # Number of cache lines fetched +system.cpu.fetch.Cycles 31179449 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 131701 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 97686537 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 470452 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.327452 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12535185 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9337821 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.110656 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 56375518 +system.cpu.fetch.rateDist.samples 46282553 system.cpu.fetch.rateDist.min_value 0 - 0 38672046 6859.72% - 1 1321940 234.49% - 2 1201428 213.11% - 3 1338454 237.42% - 4 3789980 672.27% - 5 1624217 288.11% - 6 592859 105.16% - 7 975150 172.97% - 8 6859444 1216.74% + 0 27638291 5971.64% + 1 1733920 374.64% + 2 1408099 304.24% + 3 1707036 368.83% + 4 3689148 797.09% + 5 1739866 375.92% + 6 655334 141.59% + 7 1059487 228.92% + 8 6651372 1437.12% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12534294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4593.252212 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2552.911039 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12448414 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 394468500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006852 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 85880 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 891 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 219244000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006852 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85880 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 144.958009 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency -system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses -system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12534294 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4593.252212 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency +system.cpu.icache.demand_hits 12448414 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 394468500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006852 # miss rate for demand accesses +system.cpu.icache.demand_misses 85880 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 891 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 219244000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006852 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85880 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12534294 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4593.252212 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12330467 # number of overall hits -system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses -system.cpu.icache.overall_misses 86010 # number of overall misses -system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses +system.cpu.icache.overall_hits 12448414 # number of overall hits +system.cpu.icache.overall_miss_latency 394468500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006852 # miss rate for overall accesses +system.cpu.icache.overall_misses 85880 # number of overall misses +system.cpu.icache.overall_mshr_hits 891 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 219244000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006852 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85880 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +217,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 82951 # number of replacements -system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83828 # number of replacements +system.cpu.icache.sampled_refs 85876 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use -system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1919.939531 # Cycle average of tags in use +system.cpu.icache.total_refs 12448414 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 20180672000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14196900 # Number of branches executed -system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate -system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15052480 # Number of stores executed +system.cpu.idleCycles 779486 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14215317 # Number of branches executed +system.cpu.iew.EXEC:nop 9054056 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.776804 # Inst execution rate +system.cpu.iew.EXEC:refs 36085022 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15098216 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value -system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back +system.cpu.iew.WB:consumers 41423091 # num instructions consuming a value +system.cpu.iew.WB:count 81970056 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763712 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 30345313 # num instructions producing a value -system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle -system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 31635305 # num instructions producing a value +system.cpu.iew.WB:rate 1.771079 # insts written-back per cycle +system.cpu.iew.WB:sent 82027383 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 388269 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 17461 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21578903 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4692 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 341214 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15738647 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 93782111 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 20986806 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 455724 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82235016 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2252 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 122 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 888885 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3197 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 937737 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 950 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19015 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1226 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1199504 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 894028 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19015 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 105591 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 282678 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.719692 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.719692 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 82690740 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 45892607 55.70% # Type of FU issued - IntMult 44107 0.05% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued + IntAlu 46107608 55.76% # Type of FU issued + IntMult 43061 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 116900 0.14% # Type of FU issued + FloatAdd 119602 0.14% # Type of FU issued FloatCmp 87 0.00% # Type of FU issued - FloatCvt 120453 0.15% # Type of FU issued + FloatCvt 120853 0.15% # Type of FU issued FloatMult 50 0.00% # Type of FU issued - FloatDiv 37768 0.05% # Type of FU issued + FloatDiv 37774 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21065064 25.57% # Type of FU issued - MemWrite 15116696 18.35% # Type of FU issued + MemRead 21079728 25.49% # Type of FU issued + MemWrite 15181977 18.36% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 974009 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 168043 18.71% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 90058 9.25% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +299,101 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 309725 34.49% # attempts to use FU when none available - MemWrite 420234 46.80% # attempts to use FU when none available + MemRead 437339 44.90% # attempts to use FU when none available + MemWrite 446612 45.85% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518 +system.cpu.iq.ISSUE:issued_per_cycle.samples 46282553 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 22612550 4011.06% - 1 13769796 2442.51% - 2 7834961 1389.78% - 3 4029672 714.79% - 4 3712649 658.56% - 5 1993297 353.57% - 6 1449259 257.07% - 7 434309 77.04% - 8 539025 95.61% + 0 12550048 2711.62% + 1 12875827 2782.00% + 2 7785024 1682.06% + 3 4673558 1009.79% + 4 4500672 972.43% + 5 2074677 448.26% + 6 1137561 245.79% + 7 458736 99.12% + 8 226450 48.93% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate -system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.786650 # Inst issue rate +system.cpu.iq.iqInstsAdded 84723363 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 82690740 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4692 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4940751 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53730 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3594449 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 143476 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4086.446514 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2086.446514 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 586307000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 143476 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 299355000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 143476 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147467 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4144.894478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2144.894478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 98804 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 201703000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.329992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 48663 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 104377000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.329992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 48663 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6368 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4226.366206 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2231.626884 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 26913500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 6368 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14211000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 6368 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.459748 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290943 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4101.249616 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 98804 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 788010000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.660401 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 192139 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 403732000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.660401 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 192139 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290943 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4101.249616 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 267564 # number of overall hits -system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170072 # number of overall misses +system.cpu.l2cache.overall_hits 98804 # number of overall hits +system.cpu.l2cache.overall_miss_latency 788010000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.660401 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 192139 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 403732000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.660401 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 192139 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,31 +405,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136843 # number of replacements -system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 25941 # number of replacements +system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use -system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115936 # number of writebacks -system.cpu.numCycles 56375518 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 4585.524484 # Cycle average of tags in use +system.cpu.l2cache.total_refs 102938 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 46282553 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 249890 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed -system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 36341 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 26244762 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 565515 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 115161809 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 95469817 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 57208765 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 18176186 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 888885 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 649163 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4661884 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 73667 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4695 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1420326 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4693 # count of temporary serializing insts renamed +system.cpu.timesIdled 518 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 4c8661842..878ba709b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus workload +children=dcache icache l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false @@ -24,27 +24,28 @@ max_loads_any_thread=0 phase=0 progress_interval=0 system=system +tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -52,12 +53,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -90,12 +89,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=10000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -128,12 +125,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -151,6 +146,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw @@ -174,7 +172,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 107c46644..b10e7249f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 585395 # Simulator instruction rate (inst/s) -host_mem_usage 158604 # Number of bytes of host memory used -host_seconds 150.91 # Real time elapsed on the host -host_tick_rate 839295251 # Simulator tick rate (ticks/s) +host_inst_rate 1495977 # Simulator instruction rate (inst/s) +host_mem_usage 209700 # Number of bytes of host memory used +host_seconds 59.05 # Real time elapsed on the host +host_tick_rate 2185213288 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.126657 # Number of seconds simulated -sim_ticks 126656575000 # Number of ticks simulated +sim_seconds 0.129042 # Number of seconds simulated +sim_ticks 129042205000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1273533000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1152003000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3744825000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3445239000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. @@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 23833.613541 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5018358000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses +system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 4597242000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 23833.613541 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 204343 # number of overall misses +system.cpu.dcache.overall_hits 34679457 # number of overall hits +system.cpu.dcache.overall_miss_latency 5018358000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses +system.cpu.dcache.overall_misses 210558 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 4597242000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4080.920336 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 737102000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,61 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1876.903920 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3158716000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 89695 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1045132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.346251 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 47506 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 522566000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.346251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 47506 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21989.380531 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 136664000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 147714 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 147714 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.294067 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 89695 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4203848000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.680549 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 191084 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2101924000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.680549 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 191084 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 169116 # number of overall misses +system.cpu.l2cache.overall_hits 89695 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4203848000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.680549 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 191084 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2101924000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.680549 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 191084 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -204,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 135910 # number of replacements -system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 24953 # number of replacements +system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use -system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115911 # number of writebacks +system.cpu.l2cache.tagsinuse 4393.051484 # Cycle average of tags in use +system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 126656575000 # number of cpu cycles simulated +system.cpu.numCycles 129042205000 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg index 327142d7c..472b08431 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg @@ -134,7 +134,7 @@ DB Handle Chunk's StackPtr = 20797 DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 40054800 + KERNEL in CORE[ 1] Restored @ 4005c800 OPEN File ./input/lendian.wnv *Status = 0 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index ff1b40886..5f9deac8a 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus workload +children=dcache icache l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false @@ -24,27 +24,28 @@ max_loads_any_thread=0 phase=0 progress_interval=0 system=system +tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -52,12 +53,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -90,12 +89,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=10000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -128,12 +125,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -151,6 +146,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw @@ -174,7 +172,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index bf74220de..e924e185b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 480067 # Simulator instruction rate (inst/s) -host_mem_usage 157016 # Number of bytes of host memory used -host_seconds 283.81 # Real time elapsed on the host -host_tick_rate 698858124 # Simulator tick rate (ticks/s) +host_inst_rate 1128502 # Simulator instruction rate (inst/s) +host_mem_usage 210664 # Number of bytes of host memory used +host_seconds 120.73 # Real time elapsed on the host +host_tick_rate 1658768570 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.198342 # Number of seconds simulated -sim_ticks 198341876000 # Number of ticks simulated +sim_seconds 0.200268 # Number of seconds simulated +sim_ticks 200267857000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 964329000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 873351000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20754892 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2735300000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 109412 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2516476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 109412 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. @@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency -system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 23883.829026 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57940704 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3699629000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses +system.cpu.dcache.demand_misses 154901 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 3389827000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 154901 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 23883.829026 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_misses 150663 # number of overall misses +system.cpu.dcache.overall_hits 57940704 # number of overall hits +system.cpu.dcache.overall_miss_latency 3699629000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses +system.cpu.dcache.overall_misses 154901 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 3389827000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 154901 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.106244 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 584597000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,61 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2006.859894 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 142624255000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2314158000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 105189 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1157079000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 105189 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 232513 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 191480 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 902726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.176476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 41033 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 451363000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 41033 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 4263 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.875205 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 93632000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 4263 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46893000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 4263 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 107279 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 107279 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.315911 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 191480 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3216884000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.432991 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 146222 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1608442000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.432991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 146222 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 135187 # number of overall misses +system.cpu.l2cache.overall_hits 191480 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3216884000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.432991 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 146222 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1608442000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.432991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 146222 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -214,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 101911 # number of replacements -system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 22010 # number of replacements +system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use -system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 82918 # number of writebacks +system.cpu.l2cache.tagsinuse 6146.860431 # Cycle average of tags in use +system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 198341876000 # number of cpu cycles simulated +system.cpu.numCycles 200267857000 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index c635e0e4b..862e98203 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 16:44:06 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 12 2007 12:23:15 +M5 started Sun Aug 12 16:52:13 2007 +M5 executing on zeep command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 198341876000 because target called exit() +Exiting @ tick 200267857000 because target called exit() |