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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
commitc3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch)
tree5324ebec3add54b934a841eee901983ac3463a7f /tests/long/50.vortex/ref
parentda2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff)
parent4acca8a0536d4445ed25b67edf571ae460446ab9 (diff)
downloadgem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz
Merge with the main repo.
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'tests/long/50.vortex/ref')
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt19
29 files changed, 502 insertions, 393 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index e20a60e8c..1b963b10c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index a3cf9c876..0aab67a06 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 16:45:59
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:56
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index a84fb4906..32a07ce20 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.046914 # Number of seconds simulated
sim_ticks 46914279500 # Number of ticks simulated
+final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53929 # Simulator instruction rate (inst/s)
-host_tick_rate 28639497 # Simulator tick rate (ticks/s)
-host_mem_usage 254456 # Number of bytes of host memory used
-host_seconds 1638.10 # Real time elapsed on the host
+host_inst_rate 107347 # Simulator instruction rate (inst/s)
+host_tick_rate 57007816 # Simulator tick rate (ticks/s)
+host_mem_usage 216192 # Number of bytes of host memory used
+host_seconds 822.94 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 11164096 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7712960 # Number of bytes written to this memory
+system.physmem.num_reads 174439 # Number of read requests responded to by this memory
+system.physmem.num_writes 120515 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 2f92d3206..ea038d4da 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 6c1f5182e..9e435cc97 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:08
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:35:02
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index a5baa0129..9c4b77b7d 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.021260 # Number of seconds simulated
sim_ticks 21259532000 # Number of ticks simulated
+final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184165 # Simulator instruction rate (inst/s)
-host_tick_rate 49191900 # Simulator tick rate (ticks/s)
-host_mem_usage 214460 # Number of bytes of host memory used
-host_seconds 432.18 # Real time elapsed on the host
+host_inst_rate 187781 # Simulator instruction rate (inst/s)
+host_tick_rate 50157547 # Simulator tick rate (ticks/s)
+host_mem_usage 217440 # Number of bytes of host memory used
+host_seconds 423.86 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
+system.physmem.bytes_read 11229312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7713344 # Number of bytes written to this memory
+system.physmem.num_reads 175458 # Number of read requests responded to by this memory
+system.physmem.num_writes 120521 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index d98970549..d8535707b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index c4b225cf1..160c80ddb 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:18:39
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:17
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 1ca39fde6..4fc91e266 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44221003000 # Number of ticks simulated
+final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3266324 # Simulator instruction rate (inst/s)
-host_tick_rate 1635033806 # Simulator tick rate (ticks/s)
-host_mem_usage 192576 # Number of bytes of host memory used
-host_seconds 27.05 # Real time elapsed on the host
+host_inst_rate 3998504 # Simulator instruction rate (inst/s)
+host_tick_rate 2001543652 # Simulator tick rate (ticks/s)
+host_mem_usage 206876 # Number of bytes of host memory used
+host_seconds 22.09 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 480454939 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 91652896 # Number of bytes written to this memory
+system.physmem.num_reads 108714711 # Number of read requests responded to by this memory
+system.physmem.num_writes 14613377 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10864858470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999644241 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2072610067 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12937468537 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 7e8e19e97..f99b5fb55 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index eff2b3a97..e74b48d2a 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:44:27
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 02c53f6a1..59b869a9f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.134277 # Number of seconds simulated
sim_ticks 134276988000 # Number of ticks simulated
+final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1277823 # Simulator instruction rate (inst/s)
-host_tick_rate 1942278600 # Simulator tick rate (ticks/s)
-host_mem_usage 201212 # Number of bytes of host memory used
-host_seconds 69.13 # Real time elapsed on the host
+host_inst_rate 1801981 # Simulator instruction rate (inst/s)
+host_tick_rate 2738992827 # Simulator tick rate (ticks/s)
+host_mem_usage 215584 # Number of bytes of host memory used
+host_seconds 49.02 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 11121920 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7712384 # Number of bytes written to this memory
+system.physmem.num_reads 173780 # Number of read requests responded to by this memory
+system.physmem.num_writes 120506 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
index 64e40f331..1feff9641 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index 46db9d24e..41153b9d0 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 18:34:35
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:34:51
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index ceab52925..858b9d08f 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.031183 # Number of seconds simulated
sim_ticks 31183407000 # Number of ticks simulated
+final_tick 31183407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 167832 # Simulator instruction rate (inst/s)
-host_tick_rate 52006067 # Simulator tick rate (ticks/s)
-host_mem_usage 223216 # Number of bytes of host memory used
-host_seconds 599.61 # Real time elapsed on the host
+host_inst_rate 157932 # Simulator instruction rate (inst/s)
+host_tick_rate 48938242 # Simulator tick rate (ticks/s)
+host_mem_usage 229072 # Number of bytes of host memory used
+host_seconds 637.20 # Real time elapsed on the host
sim_insts 100634165 # Number of instructions simulated
+system.physmem.bytes_read 8651648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 350016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5661184 # Number of bytes written to this memory
+system.physmem.num_reads 135182 # Number of read requests responded to by this memory
+system.physmem.num_writes 88456 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 277443962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 11224431 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 181544756 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 458988718 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index d284ed163..321a621c1 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 6efadf55b..cba7edc9e 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:19:31
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:35:25
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 7bc0f9c46..550377594 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3680206 # Simulator instruction rate (inst/s)
-host_mem_usage 260724 # Number of bytes of host memory used
-host_seconds 27.34 # Real time elapsed on the host
-host_tick_rate 1972325214 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 100632437 # Number of instructions simulated
sim_seconds 0.053932 # Number of seconds simulated
sim_ticks 53932162000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3016681 # Simulator instruction rate (inst/s)
+host_tick_rate 1616735818 # Simulator tick rate (ticks/s)
+host_mem_usage 217624 # Number of bytes of host memory used
+host_seconds 33.36 # Real time elapsed on the host
+sim_insts 100632437 # Number of instructions simulated
+system.physmem.bytes_read 419153654 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 312580308 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 78660211 # Number of bytes written to this memory
+system.physmem.num_reads 105301330 # Number of read requests responded to by this memory
+system.physmem.num_writes 19865820 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7771868185 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 5795805256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1458502832 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9230371017 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 107864325 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 107864325 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
-system.cpu.num_fp_insts 56 # number of float instructions
-system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
-system.cpu.num_func_calls 3287514 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 100632437 # Number of instructions executed
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3287514 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472788 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read
system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
-system.cpu.num_load_insts 27307109 # Number of load instructions
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_mem_refs 47862848 # number of memory refs
+system.cpu.num_load_insts 27307109 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
-system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 107864325 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 8d849c15a..62eb4cdbf 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 7b793d7b7..4fb750502 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:20:07
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:06
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 4595bb26f..2fff6cef5 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 978868 # Simulator instruction rate (inst/s)
-host_mem_usage 268480 # Number of bytes of host memory used
-host_seconds 101.95 # Real time elapsed on the host
-host_tick_rate 1305762006 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 99791663 # Number of instructions simulated
sim_seconds 0.133117 # Number of seconds simulated
sim_ticks 133117442000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 15919 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 27087368 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 52966 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1703732000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 52966 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 19742869 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5808782000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 107032 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5487686000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 47946.924337 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7671412000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003405 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 159998 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7191418000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003405 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 159998 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 46830237 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7671412000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 159998 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7191418000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003405 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 159998 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 155902 # number of replacements
-system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 122808 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1410680 # Simulator instruction rate (inst/s)
+host_tick_rate 1881780580 # Simulator tick rate (ticks/s)
+host_mem_usage 226592 # Number of bytes of host memory used
+host_seconds 70.74 # Real time elapsed on the host
+sim_insts 99791663 # Number of instructions simulated
+system.physmem.bytes_read 8570688 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5660736 # Number of bytes written to this memory
+system.physmem.num_reads 133917 # Number of read requests responded to by this memory
+system.physmem.num_writes 88449 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 64384410 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2210139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 42524375 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 106908785 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 266234884 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 99791663 # Number of instructions executed
+system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3287514 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
+system.cpu.num_int_insts 91472788 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
+system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_mem_refs 47862848 # number of memory refs
+system.cpu.num_load_insts 27307109 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 266234884 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 16890 # number of replacements
+system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use
+system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 78126170 # number of ReadReq hits
+system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 78126170 # number of overall hits
+system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
+system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 18908 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 78145078 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 78145078 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
-system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
-system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 78126170 # number of overall hits
-system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
-system.cpu.icache.overall_misses 18908 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 16890 # number of replacements
-system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use
-system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 107032 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 155902 # number of replacements
+system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 27087368 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 19742869 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 15919 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 46830237 # number of overall hits
+system.cpu.dcache.ReadReq_misses 52966 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 107032 # number of WriteReq misses
+system.cpu.dcache.demand_misses 159998 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 159998 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5808782000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7671412000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7671412000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.003405 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 47946.924337 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 122808 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 52966 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 107032 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 159998 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 159998 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1703732000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5487686000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7191418000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7191418000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005392 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.003405 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.003405 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 113660 # number of replacements
+system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 40584 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 122808 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 4405 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 5336604000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.958844 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 44989 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 44989 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 31290 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 102627 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4105080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958844 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 102627 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 71874 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 40584 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 133917 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 133917 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1627080000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.435345 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 31290 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1251600000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.435345 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 31290 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 5336604000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 6963684000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 6963684000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 71874 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 122808 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 122808 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 107032 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 178906 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.435345 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.958844 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.748533 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.748533 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 178906 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 44989 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6963684000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.748533 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 133917 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 88449 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 31290 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 102627 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 133917 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 133917 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1251600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4105080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 5356680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 5356680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.435345 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958844 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.748533 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 133917 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.748533 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 44989 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6963684000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.748533 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 133917 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5356680000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.748533 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 133917 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 113660 # number of replacements
-system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 88449 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 266234884 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 266234884 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
-system.cpu.num_fp_insts 56 # number of float instructions
-system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
-system.cpu.num_func_calls 3287514 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 99791663 # Number of instructions executed
-system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
-system.cpu.num_int_insts 91472788 # number of integer instructions
-system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
-system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
-system.cpu.num_load_insts 27307109 # Number of load instructions
-system.cpu.num_mem_refs 47862848 # number of memory refs
-system.cpu.num_store_insts 20555739 # Number of store instructions
-system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index dcd4bf473..2df6b792d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 746f2d87f..542479326 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:17:49
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:20
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 2fa280f51..dc6c31998 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148678500 # Number of ticks simulated
+final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3860753 # Simulator instruction rate (inst/s)
-host_tick_rate 1932617843 # Simulator tick rate (ticks/s)
-host_mem_usage 204428 # Number of bytes of host memory used
-host_seconds 35.26 # Real time elapsed on the host
+host_inst_rate 3420916 # Simulator instruction rate (inst/s)
+host_tick_rate 1712444497 # Simulator tick rate (ticks/s)
+host_mem_usage 214012 # Number of bytes of host memory used
+host_seconds 39.80 # Real time elapsed on the host
sim_insts 136139203 # Number of instructions simulated
+system.physmem.bytes_read 685773693 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 89882950 # Number of bytes written to this memory
+system.physmem.num_reads 171784884 # Number of read requests responded to by this memory
+system.physmem.num_writes 20864304 # Number of write requests responded to by this memory
+system.physmem.num_other 15916 # Number of other requests responded to by this memory
+system.physmem.bw_read 10062905226 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7897648844 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1318924328 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11381829554 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297358 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 51f71312a..5e34ae7a1 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index 7c4300466..787eaa97a 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:48
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 15f83a274..168a8eefa 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.202942 # Number of seconds simulated
sim_ticks 202941992000 # Number of ticks simulated
+final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2092270 # Simulator instruction rate (inst/s)
-host_tick_rate 3118935472 # Simulator tick rate (ticks/s)
-host_mem_usage 213400 # Number of bytes of host memory used
-host_seconds 65.07 # Real time elapsed on the host
+host_inst_rate 1608666 # Simulator instruction rate (inst/s)
+host_tick_rate 2398029397 # Simulator tick rate (ticks/s)
+host_mem_usage 222724 # Number of bytes of host memory used
+host_seconds 84.63 # Real time elapsed on the host
sim_insts 136139203 # Number of instructions simulated
+system.physmem.bytes_read 8970304 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5584960 # Number of bytes written to this memory
+system.physmem.num_reads 140161 # Number of read requests responded to by this memory
+system.physmem.num_writes 87265 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 44201320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4115777 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 27519982 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 71721303 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 405883984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started