diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests/long/50.vortex/ref | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests/long/50.vortex/ref')
10 files changed, 1006 insertions, 1006 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 2452e8b3b..e20a60e8c 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 78f49b74e..a3cf9c876 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 13:35:14 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:45:59 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 46960422500 because target called exit() +Exiting @ tick 46914279500 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 33754d9f7..a84fb4906 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046960 # Number of seconds simulated -sim_ticks 46960422500 # Number of ticks simulated +sim_seconds 0.046914 # Number of seconds simulated +sim_ticks 46914279500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121209 # Simulator instruction rate (inst/s) -host_tick_rate 64432457 # Simulator tick rate (ticks/s) -host_mem_usage 201704 # Number of bytes of host memory used -host_seconds 728.83 # Real time elapsed on the host +host_inst_rate 53929 # Simulator instruction rate (inst/s) +host_tick_rate 28639497 # Simulator tick rate (ticks/s) +host_mem_usage 254456 # Number of bytes of host memory used +host_seconds 1638.10 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277221 # DTB read hits +system.cpu.dtb.read_hits 20277222 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367369 # DTB read accesses +system.cpu.dtb.read_accesses 20367370 # DTB read accesses system.cpu.dtb.write_hits 14736811 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014032 # DTB hits +system.cpu.dtb.data_hits 35014033 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111432 # DTB accesses -system.cpu.itb.fetch_hits 12387546 # ITB hits -system.cpu.itb.fetch_misses 10588 # ITB misses +system.cpu.dtb.data_accesses 35111433 # DTB accesses +system.cpu.itb.fetch_hits 12380499 # ITB hits +system.cpu.itb.fetch_misses 10576 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12398134 # ITB accesses +system.cpu.itb.fetch_accesses 12391075 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93920846 # number of cpu cycles simulated +system.cpu.numCycles 93828560 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77525843 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24229643 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69691203 # Number of cycles cpu stages are processed. -system.cpu.activity 74.202061 # Percentage of cycles cpu is active +system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed. +system.cpu.activity 74.177435 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -61,212 +61,212 @@ system.cpu.comFloats 151453 # Nu system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) -system.cpu.cpi 1.063167 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.063167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.940586 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads +system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.940586 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 18775711 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12354362 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4821711 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 15677307 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4750423 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 30.301269 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8154380 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10621331 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74177297 # Number of Reads from Int. Register File +system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126496547 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65349 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292979 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14162850 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35055536 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4522867 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 188344 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4711211 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9061038 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 34.208000 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44765481 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35053135 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 41151668 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52769178 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.184735 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51441694 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42479152 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.228673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50863748 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43057098 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.844027 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71800106 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120740 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.552535 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47858752 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46062094 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.043525 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 83802 # number of replacements -system.cpu.icache.tagsinuse 1886.866724 # Cycle average of tags in use -system.cpu.icache.total_refs 12270472 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85848 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 142.932532 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 83610 # number of replacements +system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use +system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1886.866724 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.921322 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12270472 # number of ReadReq hits -system.cpu.icache.demand_hits 12270472 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12270472 # number of overall hits -system.cpu.icache.ReadReq_misses 117039 # number of ReadReq misses -system.cpu.icache.demand_misses 117039 # number of demand (read+write) misses -system.cpu.icache.overall_misses 117039 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 2068714000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 2068714000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 2068714000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12387511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12387511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12387511 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.009448 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.009448 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.009448 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 17675.424431 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 17675.424431 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 17675.424431 # average overall miss latency +system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.921317 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12263478 # number of ReadReq hits +system.cpu.icache.demand_hits 12263478 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12263478 # number of overall hits +system.cpu.icache.ReadReq_misses 116984 # number of ReadReq misses +system.cpu.icache.demand_misses 116984 # number of demand (read+write) misses +system.cpu.icache.overall_misses 116984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 2068004000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 2068004000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12380462 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12380462 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12380462 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.009449 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.009449 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.009449 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 17677.665322 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 17677.665322 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 17677.665322 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1666000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 174 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9574.712644 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 31191 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 31191 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 31191 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 85848 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 85848 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 85848 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 31328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 31328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 31328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 85656 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 85656 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 85656 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 1347366500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 1347366500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 1347366500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1345401500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1345401500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1345401500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006930 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006930 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006930 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15694.791958 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.006919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.006919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.006919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.088977 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126006 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000279 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486750000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4073.088977 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994406 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20180454 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13945552 # number of WriteReq hits -system.cpu.dcache.demand_hits 34126006 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34126006 # number of overall hits -system.cpu.dcache.ReadReq_misses 96184 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 667825 # number of WriteReq misses -system.cpu.dcache.demand_misses 764009 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 764009 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4158459500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 35331617000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 39490076500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39490076500 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4073.105766 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994411 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 20180445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13945569 # number of WriteReq hits +system.cpu.dcache.demand_hits 34126014 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 34126014 # number of overall hits +system.cpu.dcache.ReadReq_misses 96193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 667808 # number of WriteReq misses +system.cpu.dcache.demand_misses 764001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 764001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4158649000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 35332073000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 39490722000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39490722000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.021898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 43234.420486 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52905.502190 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 51687.972917 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 51687.972917 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 51689.359045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 51689.359045 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330419000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124111 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51006.107436 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 35417 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 524245 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 559662 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 559662 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 35426 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 524228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 559654 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 559654 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2088747000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 7254442500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9343189500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9343189500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2088724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7254420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9343144500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9343144500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34373.047871 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.438780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148058 # number of replacements -system.cpu.l2cache.tagsinuse 18662.722702 # Cycle average of tags in use -system.cpu.l2cache.total_refs 131525 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173403 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.758493 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 148060 # number of replacements +system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use +system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3004.603682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15658.119020 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.091693 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.477848 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 103488 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 115758 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 115758 # number of overall hits -system.cpu.l2cache.ReadReq_misses 42937 # number of ReadReq misses +system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 115564 # number of overall hits +system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 174437 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 174437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 2242217000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 174439 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9096602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9096602000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 146425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 290195 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 290195 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.293235 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.601103 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.601103 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52221.091366 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52148.351554 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52148.351554 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 120515 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 42937 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 174437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 174437 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1718546000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262803000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 6981349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 6981349000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293235 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.601103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.601103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.827072 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40021.315589 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index c10dc5f2b..7b47004d6 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 3a856c6f6..524033226 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:05:16 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:12:27 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 25567234000 because target called exit() +Exiting @ tick 24044597000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 0ff0f8618..1270e8887 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025567 # Number of seconds simulated -sim_ticks 25567234000 # Number of ticks simulated +sim_seconds 0.024045 # Number of seconds simulated +sim_ticks 24044597000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215433 # Simulator instruction rate (inst/s) -host_tick_rate 69203497 # Simulator tick rate (ticks/s) -host_mem_usage 202972 # Number of bytes of host memory used -host_seconds 369.45 # Real time elapsed on the host +host_inst_rate 91114 # Simulator instruction rate (inst/s) +host_tick_rate 27525458 # Simulator tick rate (ticks/s) +host_mem_usage 256064 # Number of bytes of host memory used +host_seconds 873.54 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 21577330 # DTB read hits -system.cpu.dtb.read_misses 171148 # DTB read misses -system.cpu.dtb.read_acv 19 # DTB read access violations -system.cpu.dtb.read_accesses 21748478 # DTB read accesses -system.cpu.dtb.write_hits 15194902 # DTB write hits -system.cpu.dtb.write_misses 30538 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15225440 # DTB write accesses -system.cpu.dtb.data_hits 36772232 # DTB hits -system.cpu.dtb.data_misses 201686 # DTB misses -system.cpu.dtb.data_acv 20 # DTB access violations -system.cpu.dtb.data_accesses 36973918 # DTB accesses -system.cpu.itb.fetch_hits 13158718 # ITB hits -system.cpu.itb.fetch_misses 26109 # ITB misses +system.cpu.dtb.read_hits 23266854 # DTB read hits +system.cpu.dtb.read_misses 225542 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 23492396 # DTB read accesses +system.cpu.dtb.write_hits 16036454 # DTB write hits +system.cpu.dtb.write_misses 32845 # DTB write misses +system.cpu.dtb.write_acv 10 # DTB write access violations +system.cpu.dtb.write_accesses 16069299 # DTB write accesses +system.cpu.dtb.data_hits 39303308 # DTB hits +system.cpu.dtb.data_misses 258387 # DTB misses +system.cpu.dtb.data_acv 55 # DTB access violations +system.cpu.dtb.data_accesses 39561695 # DTB accesses +system.cpu.itb.fetch_hits 15336941 # ITB hits +system.cpu.itb.fetch_misses 33582 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13184827 # ITB accesses +system.cpu.itb.fetch_accesses 15370523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 51134470 # number of cpu cycles simulated +system.cpu.numCycles 48089197 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 450273 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13917590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7985382 # Number of BTB hits +system.cpu.BPredUnit.lookups 18361326 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11820514 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 546274 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 16009789 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9688195 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35809 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13158718 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101571141 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16008370 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9895347 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19591284 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 555760 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 26109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 13158718 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 152584 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 50718006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.002664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.959146 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2216159 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 37765 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16493376 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 115096464 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18361326 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11904354 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22748230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3321567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5575284 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339871 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 15336941 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47646209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.415648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.066102 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 31126722 61.37% 61.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1893724 3.73% 65.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1511025 2.98% 68.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1863843 3.67% 71.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3852588 7.60% 79.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1892655 3.73% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 670633 1.32% 84.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1088115 2.15% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6818701 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897979 52.26% 52.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2453036 5.15% 57.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1946901 4.09% 61.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2330257 4.89% 66.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4220177 8.86% 75.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2180283 4.58% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 821973 1.73% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1319930 2.77% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7475673 15.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 50718006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986354 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47646209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.381818 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.393395 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17905619 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5001845 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21498707 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 855219 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2384819 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4163553 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 99872 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112485204 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 269698 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2384819 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18579816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2454161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 95593 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21627471 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2504349 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110486741 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 205 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26203 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2324239 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 66683343 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 133326137 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 132820452 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 505685 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 22491432 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 15781594 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5725093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4370544 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 88005519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4739 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 85477986 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8137764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 14136462 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5422 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5420 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5146770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24822811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 17209754 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6587978 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5178123 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97041243 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5374 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 92467963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 130783 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16243425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8385088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 791 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47646209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.940720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.968352 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15463365 32.45% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9039378 18.97% 51.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7091354 14.88% 66.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5453112 11.45% 77.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4876639 10.24% 87.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2621564 5.50% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1784714 3.75% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 964783 2.02% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351300 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47646209 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 124763 7.84% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 734633 46.19% 54.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 731207 45.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 52052276 56.29% 56.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44017 0.05% 56.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 126208 0.14% 56.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 127891 0.14% 56.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38663 0.04% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23785526 25.72% 82.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16293239 17.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued -system.cpu.iq.rate 1.671631 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 95743057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 92467963 # Type of FU issued +system.cpu.iq.rate 1.922843 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1590603 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017202 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 233677952 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 112998578 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89931166 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 625569 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 496845 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 303653 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93745634 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 312932 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1274888 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4546173 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15179 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 214045 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2596377 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1708 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97321762 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 365032 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 15781594 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 23208 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 84908070 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 21750177 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 569916 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2384819 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1408212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 65481 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 106909939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 348634 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 24822811 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 17209754 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5373 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 47651 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1257 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 214045 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 396366 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 133925 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 530291 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 91241048 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23498667 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1226915 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9311504 # number of nop insts executed -system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed -system.cpu.iew.exec_branches 14700654 # Number of branches executed -system.cpu.iew.exec_stores 15225695 # Number of stores executed -system.cpu.iew.exec_rate 1.660486 # Inst execution rate -system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 31039892 # num instructions producing a value -system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value +system.cpu.iew.exec_nop 9863322 # number of nop insts executed +system.cpu.iew.exec_refs 39568381 # number of memory reference insts executed +system.cpu.iew.exec_branches 15970661 # Number of branches executed +system.cpu.iew.exec_stores 16069714 # Number of stores executed +system.cpu.iew.exec_rate 1.897329 # Inst execution rate +system.cpu.iew.wb_sent 90664382 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 90234819 # cumulative count of insts written-back +system.cpu.iew.wb_producers 34760730 # num instructions producing a value +system.cpu.iew.wb_consumers 45726026 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back +system.cpu.iew.wb_rate 1.876405 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.760196 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15596601 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 449200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45261390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.951789 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.640164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20510945 45.32% 45.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8049130 17.78% 63.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4022759 8.89% 71.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2704759 5.98% 77.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2151725 4.75% 82.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1309190 2.89% 85.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1156461 2.56% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 811237 1.79% 89.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4545184 10.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 45261390 # Number of insts commited each cycle system.cpu.commit.count 88340672 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4545184 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 139404893 # The number of ROB reads -system.cpu.rob.rob_writes 190882895 # The number of ROB writes -system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 143336137 # The number of ROB reads +system.cpu.rob.rob_writes 210280269 # The number of ROB writes +system.cpu.timesIdled 17593 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 442988 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.642459 # CPI: Total CPI of All Threads -system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 112360564 # number of integer regfile reads -system.cpu.int_regfile_writes 55786710 # number of integer regfile writes -system.cpu.fp_regfile_reads 235864 # number of floating regfile reads -system.cpu.fp_regfile_writes 240719 # number of floating regfile writes -system.cpu.misc_regfile_reads 37825 # number of misc regfile reads +system.cpu.cpi 0.604198 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.604198 # CPI: Total CPI of All Threads +system.cpu.ipc 1.655086 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.655086 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 120263319 # number of integer regfile reads +system.cpu.int_regfile_writes 59810170 # number of integer regfile writes +system.cpu.fp_regfile_reads 254298 # number of floating regfile reads +system.cpu.fp_regfile_writes 248799 # number of floating regfile writes +system.cpu.misc_regfile_reads 38083 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 83010 # number of replacements -system.cpu.icache.tagsinuse 1916.040169 # Cycle average of tags in use -system.cpu.icache.total_refs 13070837 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85057 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 153.671503 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 13070837 # number of ReadReq hits -system.cpu.icache.demand_hits 13070837 # number of demand (read+write) hits -system.cpu.icache.overall_hits 13070837 # number of overall hits -system.cpu.icache.ReadReq_misses 87881 # number of ReadReq misses -system.cpu.icache.demand_misses 87881 # number of demand (read+write) misses -system.cpu.icache.overall_misses 87881 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 842081500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 842081500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 842081500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 13158718 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 13158718 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.006679 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.006679 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.006679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9582.065520 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9582.065520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency +system.cpu.icache.replacements 89120 # number of replacements +system.cpu.icache.tagsinuse 1938.678415 # Cycle average of tags in use +system.cpu.icache.total_refs 15241390 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 91168 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 167.179164 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19910148000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1938.678415 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.946620 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 15241390 # number of ReadReq hits +system.cpu.icache.demand_hits 15241390 # number of demand (read+write) hits +system.cpu.icache.overall_hits 15241390 # number of overall hits +system.cpu.icache.ReadReq_misses 95551 # number of ReadReq misses +system.cpu.icache.demand_misses 95551 # number of demand (read+write) misses +system.cpu.icache.overall_misses 95551 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 914249000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 914249000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 914249000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 15336941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 15336941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 15336941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.006230 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.006230 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.006230 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9568.178250 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9568.178250 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9568.178250 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,132 +343,132 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2823 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2823 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2823 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 85058 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 85058 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 85058 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 4382 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 4382 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 4382 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 91169 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 91169 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 517072500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 517072500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 517072500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 543344000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 543344000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 543344000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006464 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006464 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006464 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6079.057819 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.005944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.005944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.005944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5959.745089 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201055 # number of replacements -system.cpu.dcache.tagsinuse 4076.644885 # Cycle average of tags in use -system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205151 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.637097 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20399248 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13581325 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 33980573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 33980573 # number of overall hits -system.cpu.dcache.ReadReq_misses 160360 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1032052 # number of WriteReq misses -system.cpu.dcache.demand_misses 1192412 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1192412 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4313092000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 33595323500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 37908415500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 37908415500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20559608 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201407 # number of replacements +system.cpu.dcache.tagsinuse 4078.388125 # Cycle average of tags in use +system.cpu.dcache.total_refs 35317915 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205503 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 171.860824 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 157900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4078.388125 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995700 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 21738841 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13579023 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 51 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 35317864 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 35317864 # number of overall hits +system.cpu.dcache.ReadReq_misses 251339 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1034354 # number of WriteReq misses +system.cpu.dcache.demand_misses 1285693 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1285693 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8138657000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 33935878000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 42074535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 42074535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 21990180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 35172985 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007800 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.070624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.033901 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.033901 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31791.373703 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 36603557 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 36603557 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.011430 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.070781 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.035125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32381.194323 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 32808.765664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32725.180117 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32725.180117 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2916.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161514 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 98657 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 888604 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 987261 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 987261 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 61703 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143448 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 205151 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 205151 # number of overall MSHR misses +system.cpu.dcache.writebacks 161690 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 189291 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 890899 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1080190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1080190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 62048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 205503 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 205503 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1273620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4749061000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6022681000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6022681000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1276790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4734659000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6011449500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6011449500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009816 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005833 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005833 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002822 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005614 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005614 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20577.464221 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33004.489213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148713 # number of replacements -system.cpu.l2cache.tagsinuse 18791.098718 # Cycle average of tags in use -system.cpu.l2cache.total_refs 131477 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174075 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.755289 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 149093 # number of replacements +system.cpu.l2cache.tagsinuse 19055.908605 # Cycle average of tags in use +system.cpu.l2cache.total_refs 137732 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174459 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.789481 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 103089 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161514 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12057 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 115146 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 115146 # number of overall hits -system.cpu.l2cache.ReadReq_misses 43650 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131413 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 175063 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 175063 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1494729000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4516151000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6010880000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6010880000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 146739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161514 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143470 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 290209 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.297467 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.915962 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.603231 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.603231 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34335.524925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 3306.185097 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15749.723508 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.100897 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480643 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 109176 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 161690 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 12067 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 121243 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 121243 # number of overall hits +system.cpu.l2cache.ReadReq_misses 44033 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 131396 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 175429 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 175429 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1515312500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4525725000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 6041037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 6041037500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 153209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 161690 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 143463 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 296672 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 296672 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.287405 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.915888 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.591323 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.591323 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34413.110622 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34443.400104 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34435.797388 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34435.797388 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,27 +477,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120512 # number of writebacks +system.cpu.l2cache.writebacks 120514 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 43650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131413 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 175063 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 175063 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 44033 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 131396 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 175429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 175429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1357396500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4107073000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5464469500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5464469500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1366746000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118762500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5485508500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5485508500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.297467 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.603231 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.603231 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287405 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915888 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.591323 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.591323 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31039.129744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31346.178727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 9419f3f42..0a9838614 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,7 +494,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 8322d7ab6..396b675df 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,17 +1,11 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:12:09 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 03:29:41 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 36348210000 because target called exit() +Exiting @ tick 36244603000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index d8be31630..0a5fb1fb1 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.036348 # Number of seconds simulated -sim_ticks 36348210000 # Number of ticks simulated +sim_seconds 0.036245 # Number of seconds simulated +sim_ticks 36244603000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54516 # Simulator instruction rate (inst/s) -host_tick_rate 19691005 # Simulator tick rate (ticks/s) -host_mem_usage 264076 # Number of bytes of host memory used -host_seconds 1845.93 # Real time elapsed on the host -sim_insts 100633035 # Number of instructions simulated +host_inst_rate 68946 # Simulator instruction rate (inst/s) +host_tick_rate 24831957 # Simulator tick rate (ticks/s) +host_mem_usage 266536 # Number of bytes of host memory used +host_seconds 1459.60 # Real time elapsed on the host +sim_insts 100633890 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,296 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 72696421 # number of cpu cycles simulated +system.cpu.numCycles 72489207 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17573172 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11453458 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 851549 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14915035 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9554942 # Number of BTB hits +system.cpu.BPredUnit.lookups 18012293 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11774570 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 831874 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15324494 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9861947 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1842823 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 176515 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 11675232 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87296891 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17573172 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11397765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22503406 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 923751 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 11675232 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 177839 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71670018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.692121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.915842 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1962775 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178630 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13228591 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90356599 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18012293 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11824722 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 23464914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3236873 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 32247240 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1180 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12447619 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 228695 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71274247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.770511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.958690 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 49181996 68.62% 68.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2373056 3.31% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2569214 3.58% 75.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2298620 3.21% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1644656 2.29% 81.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1723119 2.40% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 990721 1.38% 84.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1380652 1.93% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9507984 13.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 47826013 67.10% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2503425 3.51% 70.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2625051 3.68% 74.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2508744 3.52% 77.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1756176 2.46% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1729968 2.43% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1023399 1.44% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1314592 1.84% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9986879 14.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71670018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.241734 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200842 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 25114154 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 22709447 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21527142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 497633 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1821642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3527413 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 94287 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118399354 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 324192 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1821642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26632137 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2439992 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16812666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20410601 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3552980 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115899857 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 27143 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2453549 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 118034319 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 532748209 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532647632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 100577 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99142525 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18891789 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 756618 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 756606 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 10359843 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29552116 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22027852 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13146932 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13132796 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 110916590 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 749122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 106735970 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111004 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10702418 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27336640 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 48262 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71670018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.489269 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.647816 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 71274247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248482 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.246483 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15570258 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 30538007 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21052115 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1880159 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2233708 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3555145 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100131 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123096705 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 322054 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2233708 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17831809 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3189949 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20082985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20587918 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7347878 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 119869132 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 121794 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5771428 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 121512131 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 551578616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 551477586 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 101030 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99143893 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22368233 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 776347 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 776986 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 18154637 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30367199 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22985654 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 18156398 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16040246 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 114470256 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 775996 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107895562 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 172092 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14439119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40080708 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 74965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71274247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.513809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.644216 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26697633 37.25% 37.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17182939 23.98% 61.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10552290 14.72% 75.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7611894 10.62% 86.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5202284 7.26% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2658918 3.71% 97.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1053563 1.47% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 496311 0.69% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 214186 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25395561 35.63% 35.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17825655 25.01% 60.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10968613 15.39% 76.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7406587 10.39% 86.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5364628 7.53% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2359706 3.31% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1195437 1.68% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 581224 0.82% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 176836 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71670018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71274247 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 81861 4.61% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1408075 79.27% 83.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 286311 16.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 116212 6.09% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1547826 81.16% 87.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 243196 12.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56941286 53.35% 53.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86568 0.08% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28575402 26.77% 80.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132684 19.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57756458 53.53% 53.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87061 0.08% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28748785 26.65% 80.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21303228 19.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106735970 # Type of FU issued -system.cpu.iq.rate 1.468242 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1776247 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016642 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 287029038 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122376660 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105058655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 171 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 178 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108512130 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1096048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107895562 # Type of FU issued +system.cpu.iq.rate 1.488436 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1907234 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017677 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 289144533 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129693775 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105980227 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 164 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 164 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109802713 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1086375 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2243776 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2146 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9239 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1470884 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3058688 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1951 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8954 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2428515 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1821642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 971169 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 52846 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111742721 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 886869 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29552116 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22027852 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 732058 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3681 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9239 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 680356 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 238968 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 919324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105624762 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28223458 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1111208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2233708 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1028781 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38378 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115325010 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 602761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30367199 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22985654 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 758781 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5441 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5622 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8954 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 689500 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 204403 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106692632 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28420136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1202930 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 77009 # number of nop insts executed -system.cpu.iew.exec_refs 49234670 # number of memory reference insts executed -system.cpu.iew.exec_branches 14652571 # Number of branches executed -system.cpu.iew.exec_stores 21011212 # Number of stores executed -system.cpu.iew.exec_rate 1.452957 # Inst execution rate -system.cpu.iew.wb_sent 105223313 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105058729 # cumulative count of insts written-back -system.cpu.iew.wb_producers 51964381 # num instructions producing a value -system.cpu.iew.wb_consumers 99748825 # num instructions consuming a value +system.cpu.iew.exec_nop 78758 # number of nop insts executed +system.cpu.iew.exec_refs 49527893 # number of memory reference insts executed +system.cpu.iew.exec_branches 14765827 # Number of branches executed +system.cpu.iew.exec_stores 21107757 # Number of stores executed +system.cpu.iew.exec_rate 1.471842 # Inst execution rate +system.cpu.iew.wb_sent 106228534 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105980298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 55087779 # num instructions producing a value +system.cpu.iew.wb_consumers 106077594 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.445171 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.520952 # average fanout of values written-back +system.cpu.iew.wb_rate 1.462015 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.519316 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100638587 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11026953 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 700860 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 821298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 69848377 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.440815 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.128695 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100639442 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 14606204 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 701031 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 796162 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 69040540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.457686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.138867 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31252601 44.74% 44.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 20067748 28.73% 73.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4700774 6.73% 80.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4062261 5.82% 86.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3060219 4.38% 90.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1682719 2.41% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 680213 0.97% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 487977 0.70% 94.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3853865 5.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30680365 44.44% 44.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19612880 28.41% 72.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4794365 6.94% 79.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4311364 6.24% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3142866 4.55% 90.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1355731 1.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737162 1.07% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 515807 0.75% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3890000 5.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 69848377 # Number of insts commited each cycle -system.cpu.commit.count 100638587 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 69040540 # Number of insts commited each cycle +system.cpu.commit.count 100639442 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865307 # Number of memory references committed -system.cpu.commit.loads 27308339 # Number of loads committed +system.cpu.commit.refs 47865649 # Number of memory references committed +system.cpu.commit.loads 27308510 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13669858 # Number of branches committed +system.cpu.commit.branches 13670029 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91477707 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478391 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3853865 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3890000 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 177634753 # The number of ROB reads -system.cpu.rob.rob_writes 225156428 # The number of ROB writes -system.cpu.timesIdled 61363 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1026403 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633035 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633035 # Number of Instructions Simulated -system.cpu.cpi 0.722391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.722391 # CPI: Total CPI of All Threads -system.cpu.ipc 1.384291 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.384291 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 508078422 # number of integer regfile reads -system.cpu.int_regfile_writes 103555080 # number of integer regfile writes -system.cpu.fp_regfile_reads 153 # number of floating regfile reads -system.cpu.fp_regfile_writes 125 # number of floating regfile writes -system.cpu.misc_regfile_reads 144338885 # number of misc regfile reads -system.cpu.misc_regfile_writes 34300 # number of misc regfile writes -system.cpu.icache.replacements 23105 # number of replacements -system.cpu.icache.tagsinuse 1790.585512 # Cycle average of tags in use -system.cpu.icache.total_refs 11649212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25136 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 463.447327 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 180370887 # The number of ROB reads +system.cpu.rob.rob_writes 232731384 # The number of ROB writes +system.cpu.timesIdled 61980 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1214960 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633890 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633890 # Number of Instructions Simulated +system.cpu.cpi 0.720326 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.720326 # CPI: Total CPI of All Threads +system.cpu.ipc 1.388260 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.388260 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512693416 # number of integer regfile reads +system.cpu.int_regfile_writes 104594218 # number of integer regfile writes +system.cpu.fp_regfile_reads 142 # number of floating regfile reads +system.cpu.fp_regfile_writes 118 # number of floating regfile writes +system.cpu.misc_regfile_reads 148024846 # number of misc regfile reads +system.cpu.misc_regfile_writes 34642 # number of misc regfile writes +system.cpu.icache.replacements 27879 # number of replacements +system.cpu.icache.tagsinuse 1824.272906 # Cycle average of tags in use +system.cpu.icache.total_refs 12416599 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29916 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 415.048770 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1790.585512 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.874309 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 11649212 # number of ReadReq hits -system.cpu.icache.demand_hits 11649212 # number of demand (read+write) hits -system.cpu.icache.overall_hits 11649212 # number of overall hits -system.cpu.icache.ReadReq_misses 26020 # number of ReadReq misses -system.cpu.icache.demand_misses 26020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 26020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 329928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 329928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 329928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 11675232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 11675232 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 11675232 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002229 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002229 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002229 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12679.803997 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12679.803997 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12679.803997 # average overall miss latency +system.cpu.icache.occ_blocks::0 1824.272906 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.890758 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12416599 # number of ReadReq hits +system.cpu.icache.demand_hits 12416599 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12416599 # number of overall hits +system.cpu.icache.ReadReq_misses 31020 # number of ReadReq misses +system.cpu.icache.demand_misses 31020 # number of demand (read+write) misses +system.cpu.icache.overall_misses 31020 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 368970500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 368970500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 368970500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12447619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12447619 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12447619 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002492 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002492 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002492 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 11894.600258 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 11894.600258 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 11894.600258 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,145 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 875 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 875 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 875 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 25145 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 25145 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 25145 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1093 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1093 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1093 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 29927 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 29927 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 29927 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 230769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 230769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 230769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 251359000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 251359000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 251359000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002154 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002154 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002154 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9177.530324 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8399.071073 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157197 # number of replacements -system.cpu.dcache.tagsinuse 4074.737833 # Cycle average of tags in use -system.cpu.dcache.total_refs 45133660 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161293 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 279.824047 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 314597000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4074.737833 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994809 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26793039 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18304159 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 19298 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 45097198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 45097198 # number of overall hits -system.cpu.dcache.ReadReq_misses 104208 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1545742 # number of WriteReq misses +system.cpu.dcache.replacements 157560 # number of replacements +system.cpu.dcache.tagsinuse 4075.609715 # Cycle average of tags in use +system.cpu.dcache.total_refs 45320510 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161656 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 280.351549 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 305782000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4075.609715 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995022 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26986553 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18297687 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 18928 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17320 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 45284240 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 45284240 # number of overall hits +system.cpu.dcache.ReadReq_misses 104971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1552214 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1649950 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1649950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2387617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 50445288500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 403500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 52832906000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 52832906000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 26897247 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1657185 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1657185 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2340490500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 51751425000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 435500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54091915500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54091915500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 27091524 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 19329 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46747148 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46747148 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.077872 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035295 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035295 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22912.036504 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32634.998920 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13016.129032 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32020.913361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32020.913361 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 18959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17320 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46941425 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46941425 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003875 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.078198 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001635 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22296.543807 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33340.393142 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14048.387097 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32640.843056 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32640.843056 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 170000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 165500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18888.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18388.888889 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123219 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 49816 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1438831 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 123328 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 50205 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1445313 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1488647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1488647 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54392 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106911 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 161303 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 161303 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1495518 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1495518 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 54766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106901 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 161667 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 161667 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1030956000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3651524500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4682480500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4682480500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1030464500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3652588500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4683053000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4683053000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003451 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003451 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18954.184439 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34154.806334 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18815.770734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34167.954463 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 28967.278418 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 28967.278418 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114546 # number of replacements -system.cpu.l2cache.tagsinuse 18280.291791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 68908 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133392 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.516583 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114937 # number of replacements +system.cpu.l2cache.tagsinuse 18374.975698 # Cycle average of tags in use +system.cpu.l2cache.total_refs 73734 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133793 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.551105 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2302.452210 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15977.839581 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487605 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 47261 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123219 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4298 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 51559 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 51559 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32262 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 134867 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 134867 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1107753000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3528908000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4636661000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4636661000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 79523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123219 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 9 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106903 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 186426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 186426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.405694 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.444444 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959795 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.723434 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.723434 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34336.153989 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 8500 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34393.138736 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34379.507218 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34379.507218 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2397.200904 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15977.774794 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.073157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487603 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 51991 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123328 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4303 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 56294 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 56294 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32687 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 7 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102588 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1117411000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3525778500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4643189500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4643189500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 84678 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123328 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106891 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 191569 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 191569 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.386015 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959744 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.706142 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.706142 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34185.180653 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.332554 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34324.076880 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34324.076880 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88455 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 63 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32199 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 134804 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 134804 # number of overall MSHR misses +system.cpu.l2cache.writebacks 88452 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32606 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102588 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135194 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1001736500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205255000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4206991500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4206991500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1012684500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 217000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200382500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4213067000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4213067000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.444444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959795 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.723097 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.723097 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31110.795366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.385059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959744 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.705720 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.705720 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.225480 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.779787 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31196.460600 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.121144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.121144 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |