diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
| commit | f125ef22b997d5ba6173d9d3f0d07ae741e279bd (patch) | |
| tree | d3d103939211116d7f8ed7e04db73fbac0b9e9be /tests/long/50.vortex | |
| parent | d0e04859023702ec23c97683700c638949a1dad1 (diff) | |
| download | gem5-f125ef22b997d5ba6173d9d3f0d07ae741e279bd.tar.xz | |
O3: Update stats for LSQ changes.
Diffstat (limited to 'tests/long/50.vortex')
5 files changed, 803 insertions, 801 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 524033226..50848dbff 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 17:12:27 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 19:00:26 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24044597000 because target called exit() +Exiting @ tick 22743377000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 1270e8887..f7387c5fb 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024045 # Number of seconds simulated -sim_ticks 24044597000 # Number of ticks simulated +sim_seconds 0.022743 # Number of seconds simulated +sim_ticks 22743377000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91114 # Simulator instruction rate (inst/s) -host_tick_rate 27525458 # Simulator tick rate (ticks/s) -host_mem_usage 256064 # Number of bytes of host memory used -host_seconds 873.54 # Real time elapsed on the host +host_inst_rate 91653 # Simulator instruction rate (inst/s) +host_tick_rate 26189824 # Simulator tick rate (ticks/s) +host_mem_usage 255808 # Number of bytes of host memory used +host_seconds 868.41 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23266854 # DTB read hits -system.cpu.dtb.read_misses 225542 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 23492396 # DTB read accesses -system.cpu.dtb.write_hits 16036454 # DTB write hits -system.cpu.dtb.write_misses 32845 # DTB write misses -system.cpu.dtb.write_acv 10 # DTB write access violations -system.cpu.dtb.write_accesses 16069299 # DTB write accesses -system.cpu.dtb.data_hits 39303308 # DTB hits -system.cpu.dtb.data_misses 258387 # DTB misses -system.cpu.dtb.data_acv 55 # DTB access violations -system.cpu.dtb.data_accesses 39561695 # DTB accesses -system.cpu.itb.fetch_hits 15336941 # ITB hits -system.cpu.itb.fetch_misses 33582 # ITB misses +system.cpu.dtb.read_hits 21751129 # DTB read hits +system.cpu.dtb.read_misses 175370 # DTB read misses +system.cpu.dtb.read_acv 31 # DTB read access violations +system.cpu.dtb.read_accesses 21926499 # DTB read accesses +system.cpu.dtb.write_hits 15297508 # DTB write hits +system.cpu.dtb.write_misses 26341 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15323849 # DTB write accesses +system.cpu.dtb.data_hits 37048637 # DTB hits +system.cpu.dtb.data_misses 201711 # DTB misses +system.cpu.dtb.data_acv 37 # DTB access violations +system.cpu.dtb.data_accesses 37250348 # DTB accesses +system.cpu.itb.fetch_hits 14100005 # ITB hits +system.cpu.itb.fetch_misses 36420 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15370523 # ITB accesses +system.cpu.itb.fetch_accesses 14136425 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 48089197 # number of cpu cycles simulated +system.cpu.numCycles 45486755 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18361326 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11820514 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 546274 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 16009789 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9688195 # Number of BTB hits +system.cpu.BPredUnit.lookups 16901328 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10975275 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 456849 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 14797141 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8724675 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2216159 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 37765 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16493376 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 115096464 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18361326 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11904354 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22748230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3321567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5575284 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339871 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 15336941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325972 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47646209 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.415648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.066102 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2018610 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 35075 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15142621 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 107619262 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16901328 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10743285 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20909720 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2286025 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6121858 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 13576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 358341 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14100005 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 211722 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44264196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.431294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.090704 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24897979 52.26% 52.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2453036 5.15% 57.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1946901 4.09% 61.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2330257 4.89% 66.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4220177 8.86% 75.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2180283 4.58% 79.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 821973 1.73% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1319930 2.77% 84.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7475673 15.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23354476 52.76% 52.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2087705 4.72% 57.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1683152 3.80% 61.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2128946 4.81% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3922871 8.86% 74.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1978801 4.47% 79.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 718343 1.62% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1236348 2.79% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7153554 16.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47646209 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.381818 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.393395 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17905619 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5001845 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21498707 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 855219 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2384819 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4163553 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99872 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112485204 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 269698 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2384819 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18579816 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2454161 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 95593 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21627471 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2504349 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110486741 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 205 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26203 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2324239 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 66683343 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 133326137 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 132820452 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 505685 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44264196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.371566 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.365947 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16625814 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5350938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19481362 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1184271 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1621811 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3792639 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98494 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 105768441 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 262977 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1621811 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17249190 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1859026 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 92496 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19962312 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3479361 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 104444741 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62263 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3183210 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62854370 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 126007838 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 125513406 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 494432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14136462 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5422 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5420 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5146770 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24822811 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 17209754 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6587978 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5178123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97041243 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5374 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 92467963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 130783 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16243425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8385088 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 791 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47646209 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.940720 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.968352 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10307489 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5394 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5392 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7022840 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23585547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16625780 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13013966 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10091747 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 92564607 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5349 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 87311286 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89819 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12800874 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8559564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44264196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.972504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.848460 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15463365 32.45% 32.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9039378 18.97% 51.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7091354 14.88% 66.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5453112 11.45% 77.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4876639 10.24% 87.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2621564 5.50% 93.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1784714 3.75% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 964783 2.02% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 351300 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12024331 27.16% 27.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9739894 22.00% 49.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7505625 16.96% 66.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5587744 12.62% 78.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4605636 10.40% 89.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2526104 5.71% 94.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1401834 3.17% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 651382 1.47% 99.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 221646 0.50% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47646209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44264196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 124763 7.84% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 734633 46.19% 54.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 731207 45.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 145655 11.21% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 556077 42.81% 54.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 597272 45.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 52052276 56.29% 56.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44017 0.05% 56.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 126208 0.14% 56.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 127891 0.14% 56.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38663 0.04% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23785526 25.72% 82.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16293239 17.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49414746 56.60% 56.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43477 0.05% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 125010 0.14% 56.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 125425 0.14% 56.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38600 0.04% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22113935 25.33% 82.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15449954 17.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 92467963 # Type of FU issued -system.cpu.iq.rate 1.922843 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1590603 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017202 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 233677952 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 112998578 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89931166 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 625569 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 496845 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 303653 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93745634 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 312932 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1274888 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 87311286 # Type of FU issued +system.cpu.iq.rate 1.919488 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1299004 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014878 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 219655218 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104890132 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85660866 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 620373 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 492550 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 303658 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 88299901 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 310389 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470541 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4546173 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15179 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 214045 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2596377 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3308909 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2159 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11951 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2012403 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1708 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2384819 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1408212 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 65481 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 106909939 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 348634 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24822811 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 17209754 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5373 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 47651 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1257 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 214045 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 396366 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 133925 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 530291 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 91241048 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23498667 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1226915 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1621811 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 650255 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46881 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 102207113 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299211 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23585547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16625780 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5349 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10530 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7811 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11951 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 297237 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 113949 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 411186 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 86536224 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 21928950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 775062 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9863322 # number of nop insts executed -system.cpu.iew.exec_refs 39568381 # number of memory reference insts executed -system.cpu.iew.exec_branches 15970661 # Number of branches executed -system.cpu.iew.exec_stores 16069714 # Number of stores executed -system.cpu.iew.exec_rate 1.897329 # Inst execution rate -system.cpu.iew.wb_sent 90664382 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 90234819 # cumulative count of insts written-back -system.cpu.iew.wb_producers 34760730 # num instructions producing a value -system.cpu.iew.wb_consumers 45726026 # num instructions consuming a value +system.cpu.iew.exec_nop 9637157 # number of nop insts executed +system.cpu.iew.exec_refs 37253187 # number of memory reference insts executed +system.cpu.iew.exec_branches 15011802 # Number of branches executed +system.cpu.iew.exec_stores 15324237 # Number of stores executed +system.cpu.iew.exec_rate 1.902449 # Inst execution rate +system.cpu.iew.wb_sent 86279934 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85964524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 34688342 # num instructions producing a value +system.cpu.iew.wb_consumers 46291790 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.876405 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.760196 # average fanout of values written-back +system.cpu.iew.wb_rate 1.889880 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.749341 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 15596601 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11023437 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 449200 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45261390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.951789 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.640164 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 360580 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42642385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.071663 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.676209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20510945 45.32% 45.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8049130 17.78% 63.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4022759 8.89% 71.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2704759 5.98% 77.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2151725 4.75% 82.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1309190 2.89% 85.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1156461 2.56% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 811237 1.79% 89.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4545184 10.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17681432 41.46% 41.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8356070 19.60% 61.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3960782 9.29% 70.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2934126 6.88% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1908842 4.48% 81.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1271711 2.98% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1063495 2.49% 87.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 841649 1.97% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4624278 10.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45261390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42642385 # Number of insts commited each cycle system.cpu.commit.count 88340672 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4545184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4624278 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 143336137 # The number of ROB reads -system.cpu.rob.rob_writes 210280269 # The number of ROB writes -system.cpu.timesIdled 17593 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 442988 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 136064874 # The number of ROB reads +system.cpu.rob.rob_writes 200355381 # The number of ROB writes +system.cpu.timesIdled 41664 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1222559 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.604198 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.604198 # CPI: Total CPI of All Threads -system.cpu.ipc 1.655086 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.655086 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 120263319 # number of integer regfile reads -system.cpu.int_regfile_writes 59810170 # number of integer regfile writes -system.cpu.fp_regfile_reads 254298 # number of floating regfile reads -system.cpu.fp_regfile_writes 248799 # number of floating regfile writes -system.cpu.misc_regfile_reads 38083 # number of misc regfile reads +system.cpu.cpi 0.571501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.571501 # CPI: Total CPI of All Threads +system.cpu.ipc 1.749779 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.749779 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 114385631 # number of integer regfile reads +system.cpu.int_regfile_writes 57104236 # number of integer regfile writes +system.cpu.fp_regfile_reads 255197 # number of floating regfile reads +system.cpu.fp_regfile_writes 247532 # number of floating regfile writes +system.cpu.misc_regfile_reads 38059 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 89120 # number of replacements -system.cpu.icache.tagsinuse 1938.678415 # Cycle average of tags in use -system.cpu.icache.total_refs 15241390 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 91168 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 167.179164 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19910148000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1938.678415 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.946620 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 15241390 # number of ReadReq hits -system.cpu.icache.demand_hits 15241390 # number of demand (read+write) hits -system.cpu.icache.overall_hits 15241390 # number of overall hits -system.cpu.icache.ReadReq_misses 95551 # number of ReadReq misses -system.cpu.icache.demand_misses 95551 # number of demand (read+write) misses -system.cpu.icache.overall_misses 95551 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 914249000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 914249000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 914249000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 15336941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 15336941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 15336941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.006230 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.006230 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.006230 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9568.178250 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9568.178250 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9568.178250 # average overall miss latency +system.cpu.icache.replacements 89406 # number of replacements +system.cpu.icache.tagsinuse 1932.641583 # Cycle average of tags in use +system.cpu.icache.total_refs 14004218 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 91454 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 153.128545 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18957437000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1932.641583 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.943673 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 14004218 # number of ReadReq hits +system.cpu.icache.demand_hits 14004218 # number of demand (read+write) hits +system.cpu.icache.overall_hits 14004218 # number of overall hits +system.cpu.icache.ReadReq_misses 95787 # number of ReadReq misses +system.cpu.icache.demand_misses 95787 # number of demand (read+write) misses +system.cpu.icache.overall_misses 95787 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 913804000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 913804000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 913804000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 14100005 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 14100005 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 14100005 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.006793 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.006793 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.006793 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9539.958449 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9539.958449 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9539.958449 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,132 +343,132 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 4382 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 4382 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 4382 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 91169 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 91169 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 4332 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 4332 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 4332 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 91455 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 91455 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 91455 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 543344000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 543344000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 543344000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 543662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 543662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 543662500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.005944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.005944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.005944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5959.745089 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.006486 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.006486 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.006486 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5944.590236 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5944.590236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5944.590236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201407 # number of replacements -system.cpu.dcache.tagsinuse 4078.388125 # Cycle average of tags in use -system.cpu.dcache.total_refs 35317915 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205503 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 171.860824 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 157900000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4078.388125 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995700 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 21738841 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13579023 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 51 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 35317864 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 35317864 # number of overall hits -system.cpu.dcache.ReadReq_misses 251339 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1034354 # number of WriteReq misses -system.cpu.dcache.demand_misses 1285693 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1285693 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8138657000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 33935878000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 42074535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 42074535000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 21990180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201138 # number of replacements +system.cpu.dcache.tagsinuse 4077.454255 # Cycle average of tags in use +system.cpu.dcache.total_refs 33705391 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205234 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 164.229080 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 157412000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4077.454255 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995472 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 20126386 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13578957 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 48 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 33705343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 33705343 # number of overall hits +system.cpu.dcache.ReadReq_misses 152658 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1034420 # number of WriteReq misses +system.cpu.dcache.demand_misses 1187078 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1187078 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4522200000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 33957528000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 38479728000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 38479728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 20279044 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 36603557 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 36603557 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.011430 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.070781 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.035125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32381.194323 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32808.765664 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32725.180117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32725.180117 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 48 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 34892421 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 34892421 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.007528 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.070786 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.034021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.034021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 29623.079039 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 32827.601941 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32415.500919 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32415.500919 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2916.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2722.222222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161690 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 189291 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 890899 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1080190 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1080190 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 62048 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 205503 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 205503 # number of overall MSHR misses +system.cpu.dcache.writebacks 161549 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 90911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 890933 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 981844 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 981844 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 61747 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 143487 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 205234 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 205234 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1276790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4734659000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6011449500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6011449500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1261220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4731766000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5992986000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5992986000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002822 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005614 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005614 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20577.464221 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33004.489213 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009819 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005882 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005882 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20425.607722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32976.966554 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29200.746465 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29200.746465 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 149093 # number of replacements -system.cpu.l2cache.tagsinuse 19055.908605 # Cycle average of tags in use -system.cpu.l2cache.total_refs 137732 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174459 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.789481 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 148998 # number of replacements +system.cpu.l2cache.tagsinuse 18953.465492 # Cycle average of tags in use +system.cpu.l2cache.total_refs 137682 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174354 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.789669 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3306.185097 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15749.723508 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.100897 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.480643 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 109176 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161690 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12067 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 121243 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 121243 # number of overall hits -system.cpu.l2cache.ReadReq_misses 44033 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131396 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 175429 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 175429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1515312500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4525725000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6041037500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6041037500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 153209 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161690 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143463 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 296672 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 296672 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.287405 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.915888 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.591323 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.591323 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34413.110622 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34443.400104 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34435.797388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34435.797388 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 3229.937002 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15723.528490 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.098570 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.479844 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 109274 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 161549 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 12075 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 121349 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 121349 # number of overall hits +system.cpu.l2cache.ReadReq_misses 43926 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 131414 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 175340 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 175340 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1500006000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4522435500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 6022441500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 6022441500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 153200 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 161549 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 296689 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 296689 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.286723 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.915847 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.590989 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.590989 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34148.476984 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34413.650753 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34347.219687 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34347.219687 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,24 +480,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 120514 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 44033 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131396 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 175429 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 175429 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 43926 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 131414 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 175340 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 175340 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1366746000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118762500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5485508500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5485508500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1363479000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4116799500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5480278500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5480278500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287405 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915888 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.591323 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.591323 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31039.129744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31346.178727 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.286723 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915847 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.590989 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.590989 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.363338 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.947662 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31255.152846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31255.152846 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 02f7c240f..6d7c0bcb0 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -499,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index e55995a7b..46c2d0591 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 6 2011 16:04:36 -gem5 started Aug 6 2011 16:04:41 -gem5 executing on burrito +gem5 compiled Aug 16 2011 09:57:35 +gem5 started Aug 16 2011 10:08:58 +gem5 executing on nadc-0270 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 36244602000 because target called exit() +Exiting @ tick 36358325000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index bf47534bc..95c5d6049 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.036245 # Number of seconds simulated -sim_ticks 36244602000 # Number of ticks simulated +sim_seconds 0.036358 # Number of seconds simulated +sim_ticks 36358325000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65776 # Simulator instruction rate (inst/s) -host_tick_rate 23690223 # Simulator tick rate (ticks/s) -host_mem_usage 246996 # Number of bytes of host memory used -host_seconds 1529.94 # Real time elapsed on the host -sim_insts 100633890 # Number of instructions simulated +host_inst_rate 119827 # Simulator instruction rate (inst/s) +host_tick_rate 43292688 # Simulator tick rate (ticks/s) +host_mem_usage 272264 # Number of bytes of host memory used +host_seconds 839.83 # Real time elapsed on the host +sim_insts 100633775 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 72489205 # number of cpu cycles simulated +system.cpu.numCycles 72716651 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18012293 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11774570 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 831874 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15324494 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9861947 # Number of BTB hits +system.cpu.BPredUnit.lookups 18013375 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11772112 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 832376 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15327252 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9900840 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1962775 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 178630 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13228591 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90356599 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18012293 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11824722 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 23464914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3236872 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 32247240 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1180 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12447619 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 228695 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71274246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.770512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.958690 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1964037 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178584 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13247418 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90436613 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18013375 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11864877 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 23481643 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3251985 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 32424598 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1373 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12458457 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221175 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71500308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.766045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.955660 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 47826012 67.10% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2503425 3.51% 70.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2625051 3.68% 74.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2508744 3.52% 77.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1756176 2.46% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1729968 2.43% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1023399 1.44% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1314592 1.84% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9986879 14.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 48035418 67.18% 67.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2508903 3.51% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2594650 3.63% 74.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2541855 3.56% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1760239 2.46% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1724167 2.41% 82.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1024110 1.43% 84.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1345153 1.88% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9965813 13.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71274246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248482 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.246484 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15570258 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 30538007 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21052115 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1880159 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2233707 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3555145 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100131 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123096705 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 322054 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2233707 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17831809 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3189949 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20082985 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20587918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7347878 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 119869132 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 121794 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5771428 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 121512131 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 551578616 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 551477586 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 101030 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99143893 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22368233 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 776347 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 776986 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 18154637 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30367199 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22985654 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 18156398 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16040246 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 114470256 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 775996 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107895564 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 172091 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14439119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 40080699 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 74965 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71274246 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.513809 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.644216 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 71500308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247720 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.243685 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15629487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 30668783 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20991644 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1963924 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2246470 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3557308 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100615 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123225405 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 322834 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2246470 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17904325 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3174295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20084450 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20590055 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7500713 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 119940984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 135288 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5895117 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 121539560 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 551911893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 551809859 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 102034 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99143709 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22395801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 778680 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 778694 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 18433689 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30390382 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 23021081 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 18365996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16439244 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 114579507 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 778229 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107939670 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 154653 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14553196 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40300795 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 77221 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71500308 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.509639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.632123 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25395561 35.63% 35.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17825654 25.01% 60.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10968613 15.39% 76.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7406584 10.39% 86.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5364631 7.53% 93.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2359706 3.31% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1195437 1.68% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 581224 0.82% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 176836 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25383976 35.50% 35.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17917807 25.06% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 11054386 15.46% 76.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7575334 10.59% 86.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5467314 7.65% 94.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2200256 3.08% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1169231 1.64% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 554865 0.78% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 177139 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71274246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71500308 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 116212 6.09% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1547826 81.16% 87.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 243196 12.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 116974 6.43% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1491133 81.95% 88.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 211505 11.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57756459 53.53% 53.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87061 0.08% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28748786 26.65% 80.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21303228 19.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57828785 53.58% 53.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87098 0.08% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 50 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 3 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28711971 26.60% 80.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21311756 19.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107895564 # Type of FU issued -system.cpu.iq.rate 1.488436 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1907234 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017677 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 289144535 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129693775 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105980229 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 164 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 164 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109802715 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1086375 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107939670 # Type of FU issued +system.cpu.iq.rate 1.484387 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1819612 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016858 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 289353682 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921210 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106049922 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 300 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109759169 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1061783 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3058688 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1951 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8954 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2428515 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3081882 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2255 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10977 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2463953 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2233707 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1028781 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38378 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115325010 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 602761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30367199 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22985654 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 758781 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5441 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5622 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8954 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 689500 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 204403 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 893903 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106692633 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28420136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1202931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2246470 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1025437 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38382 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115436550 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 596020 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30390382 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 23021081 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 761032 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4943 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5670 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10977 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 689404 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 204972 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 894376 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106732644 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28388861 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1207019 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 78758 # number of nop insts executed -system.cpu.iew.exec_refs 49527893 # number of memory reference insts executed -system.cpu.iew.exec_branches 14765827 # Number of branches executed -system.cpu.iew.exec_stores 21107757 # Number of stores executed -system.cpu.iew.exec_rate 1.471842 # Inst execution rate -system.cpu.iew.wb_sent 106228536 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105980300 # cumulative count of insts written-back -system.cpu.iew.wb_producers 55087780 # num instructions producing a value -system.cpu.iew.wb_consumers 106077595 # num instructions consuming a value +system.cpu.iew.exec_nop 78814 # number of nop insts executed +system.cpu.iew.exec_refs 49502432 # number of memory reference insts executed +system.cpu.iew.exec_branches 14773493 # Number of branches executed +system.cpu.iew.exec_stores 21113571 # Number of stores executed +system.cpu.iew.exec_rate 1.467788 # Inst execution rate +system.cpu.iew.wb_sent 106273270 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106050012 # cumulative count of insts written-back +system.cpu.iew.wb_producers 55103842 # num instructions producing a value +system.cpu.iew.wb_consumers 106001150 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.462015 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.519316 # average fanout of values written-back +system.cpu.iew.wb_rate 1.458401 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.519842 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100639442 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 14606204 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 701031 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 796162 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 69040540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.457686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.138867 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100639327 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 14717021 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 701008 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 796431 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 69253839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.453195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.128132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30680365 44.44% 44.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19612880 28.41% 72.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4794365 6.94% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4311364 6.24% 86.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3142866 4.55% 90.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1355731 1.96% 92.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 737162 1.07% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 515807 0.75% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3890000 5.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30742933 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19764540 28.54% 72.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4768337 6.89% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4180096 6.04% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3349632 4.84% 90.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1422305 2.05% 92.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 712095 1.03% 93.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 496006 0.72% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3817895 5.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 69040540 # Number of insts commited each cycle -system.cpu.commit.count 100639442 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 69253839 # Number of insts commited each cycle +system.cpu.commit.count 100639327 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865649 # Number of memory references committed -system.cpu.commit.loads 27308510 # Number of loads committed +system.cpu.commit.refs 47865603 # Number of memory references committed +system.cpu.commit.loads 27308487 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670029 # Number of branches committed +system.cpu.commit.branches 13670006 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478391 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478299 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3890000 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3817895 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180370887 # The number of ROB reads -system.cpu.rob.rob_writes 232731383 # The number of ROB writes -system.cpu.timesIdled 61980 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1214959 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633890 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633890 # Number of Instructions Simulated -system.cpu.cpi 0.720326 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.720326 # CPI: Total CPI of All Threads -system.cpu.ipc 1.388260 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.388260 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512693420 # number of integer regfile reads -system.cpu.int_regfile_writes 104594221 # number of integer regfile writes -system.cpu.fp_regfile_reads 142 # number of floating regfile reads -system.cpu.fp_regfile_writes 118 # number of floating regfile writes -system.cpu.misc_regfile_reads 148024846 # number of misc regfile reads -system.cpu.misc_regfile_writes 34642 # number of misc regfile writes -system.cpu.icache.replacements 27879 # number of replacements -system.cpu.icache.tagsinuse 1824.272942 # Cycle average of tags in use -system.cpu.icache.total_refs 12416599 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29916 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 415.048770 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 180766993 # The number of ROB reads +system.cpu.rob.rob_writes 232965550 # The number of ROB writes +system.cpu.timesIdled 61914 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1216343 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633775 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633775 # Number of Instructions Simulated +system.cpu.cpi 0.722587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.722587 # CPI: Total CPI of All Threads +system.cpu.ipc 1.383917 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.383917 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512803523 # number of integer regfile reads +system.cpu.int_regfile_writes 104642569 # number of integer regfile writes +system.cpu.fp_regfile_reads 286 # number of floating regfile reads +system.cpu.fp_regfile_writes 254 # number of floating regfile writes +system.cpu.misc_regfile_reads 148108878 # number of misc regfile reads +system.cpu.misc_regfile_writes 34596 # number of misc regfile writes +system.cpu.icache.replacements 27541 # number of replacements +system.cpu.icache.tagsinuse 1822.972635 # Cycle average of tags in use +system.cpu.icache.total_refs 12427797 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29578 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 420.170295 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1824.272942 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.890758 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12416599 # number of ReadReq hits -system.cpu.icache.demand_hits 12416599 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12416599 # number of overall hits -system.cpu.icache.ReadReq_misses 31020 # number of ReadReq misses -system.cpu.icache.demand_misses 31020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 31020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 368970500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 368970500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 368970500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12447619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12447619 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12447619 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002492 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002492 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002492 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 11894.600258 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 11894.600258 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 11894.600258 # average overall miss latency +system.cpu.icache.occ_blocks::0 1822.972635 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.890123 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12427797 # number of ReadReq hits +system.cpu.icache.demand_hits 12427797 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12427797 # number of overall hits +system.cpu.icache.ReadReq_misses 30660 # number of ReadReq misses +system.cpu.icache.demand_misses 30660 # number of demand (read+write) misses +system.cpu.icache.overall_misses 30660 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 366375500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 366375500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 366375500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12458457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12458457 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12458457 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002461 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002461 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002461 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 11949.624918 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 11949.624918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 11949.624918 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,143 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1093 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1093 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1093 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 29927 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 29927 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 29927 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1075 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1075 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1075 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 29585 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 29585 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 29585 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 251359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 251359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 251359000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 250083000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 250083000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 250083000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002404 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002404 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002404 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8399.071073 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002375 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002375 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002375 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8453.033632 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8453.033632 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8453.033632 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157559 # number of replacements -system.cpu.dcache.tagsinuse 4075.605702 # Cycle average of tags in use -system.cpu.dcache.total_refs 45320510 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161655 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 280.353283 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305781000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4075.605702 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995021 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26986553 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18297687 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 18928 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17320 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 45284240 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 45284240 # number of overall hits -system.cpu.dcache.ReadReq_misses 104970 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1552214 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1657184 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1657184 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2340452000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 51751426000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 435500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54091878000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54091878000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 27091523 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 157556 # number of replacements +system.cpu.dcache.tagsinuse 4075.680070 # Cycle average of tags in use +system.cpu.dcache.total_refs 45321004 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161652 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 280.361542 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 307509000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4075.680070 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995039 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26986530 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18297810 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 19355 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17297 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 45284340 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 45284340 # number of overall hits +system.cpu.dcache.ReadReq_misses 104939 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1552091 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1657030 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1657030 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2337604500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 51739462000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 386500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54077066500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54077066500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 27091469 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 18959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17320 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46941424 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46941424 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003875 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.078198 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001635 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035303 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22296.389445 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33340.393786 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14048.387097 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32640.840124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32640.840124 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 19382 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17297 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46941370 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46941370 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.078191 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035300 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035300 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22275.841203 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33335.327632 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14314.814815 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32634.935095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32634.935095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 165500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18388.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18444.444444 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123328 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 50205 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1445313 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1495518 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1495518 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54765 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106901 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 161666 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 161666 # number of overall MSHR misses +system.cpu.dcache.writebacks 123342 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 50191 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1445181 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1495372 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1495372 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 54748 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106910 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 161658 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 161658 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1030429000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3652589000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4683018000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4683018000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1029521500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3652232000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4681753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4681753500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18815.466082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34167.959140 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28967.241102 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28967.241102 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18804.732593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34161.743523 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 28960.852541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 28960.852541 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114936 # number of replacements -system.cpu.l2cache.tagsinuse 18374.970937 # Cycle average of tags in use -system.cpu.l2cache.total_refs 73734 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133792 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.551109 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114899 # number of replacements +system.cpu.l2cache.tagsinuse 18376.822812 # Cycle average of tags in use +system.cpu.l2cache.total_refs 73444 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133749 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.549118 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2397.195703 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15977.775235 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.073157 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487603 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 51991 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123328 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4303 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 56294 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 56294 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32686 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 7 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102588 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 135274 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 135274 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1117376500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3525779000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4643155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4643155500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 84677 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123328 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106891 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 191568 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 191568 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.386008 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959744 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.706141 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.706141 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34185.171021 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.337427 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34324.079276 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34324.079276 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2396.199422 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15980.623390 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.073126 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487690 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 51683 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123342 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 55992 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 55992 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32640 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102597 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135237 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135237 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1115857000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3525923000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4641780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4641780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 84323 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123342 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106906 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 191229 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 191229 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.387083 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.707199 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.707199 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34186.795343 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.726123 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34323.299097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34323.299097 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88452 # number of writebacks +system.cpu.l2cache.writebacks 88453 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32605 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102588 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135193 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135193 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32559 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135156 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1012653500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 217000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200382500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4213036000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4213036000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1011231500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200947000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4212178500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4212178500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.385051 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959744 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.705718 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.705718 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.227266 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.386122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.706776 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.706776 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.432384 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31196.460600 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.122351 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.122351 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31199.226098 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.308976 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.308976 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |