diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
| commit | 5d5b0f49cc125973fb7048ad86bf85ab5ed57772 (patch) | |
| tree | 0840a5055d8d8103eb22bcbe1ad90498e3db8aee /tests/long/50.vortex | |
| parent | d0b0a555151232566550c837f9d4d061bf3d4686 (diff) | |
| download | gem5-5d5b0f49cc125973fb7048ad86bf85ab5ed57772.tar.xz | |
Stats: Update stats for minor O3 changes below.
Diffstat (limited to 'tests/long/50.vortex')
| -rwxr-xr-x | tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1009 |
2 files changed, 509 insertions, 508 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index f10c82a79..8322d7ab6 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -7,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 4 2011 13:56:47 -M5 started May 4 2011 15:24:46 -M5 executing on nadc-0364 +M5 compiled May 16 2011 15:11:25 +M5 started May 16 2011 15:12:09 +M5 executing on nadc-0271 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 36353754500 because target called exit() +Exiting @ tick 36348210000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index cef2ea6da..d8be31630 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,530 +1,531 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 214709 # Simulator instruction rate (inst/s) -host_mem_usage 270620 # Number of bytes of host memory used -host_seconds 468.69 # Real time elapsed on the host -host_tick_rate 77563856 # Simulator tick rate (ticks/s) +sim_seconds 0.036348 # Number of seconds simulated +sim_ticks 36348210000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 100633040 # Number of instructions simulated -sim_seconds 0.036354 # Number of seconds simulated -sim_ticks 36353754500 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9550734 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14928040 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 176432 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 851746 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11455775 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 17580538 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1841093 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 821012 # The number of times a branch was mispredicted -system.cpu.commit.branches 13669859 # Number of branches committed -system.cpu.commit.bw_lim_events 3808519 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 100638592 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 700861 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 11103325 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 69924626 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.439244 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.122917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31252926 44.70% 44.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 20119479 28.77% 73.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4663386 6.67% 80.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4133493 5.91% 86.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3064979 4.38% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1713503 2.45% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 682108 0.98% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 486233 0.70% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3808519 5.45% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 69924626 # Number of insts commited each cycle -system.cpu.commit.count 100638592 # Number of instructions committed -system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.int_insts 91477711 # Number of committed integer instructions. -system.cpu.commit.loads 27308340 # Number of loads committed -system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.refs 47865309 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 100633040 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633040 # Number of Instructions Simulated -system.cpu.cpi 0.722501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.722501 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 18710 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13233.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 18680 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 397000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.001603 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 30 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 30 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 26887551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22428.849743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18951.207188 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 26783609 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2331299500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003866 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 103942 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 49518 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1031400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54424 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 17150 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 17150 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32635.826769 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34153.814138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18303641 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 50463473500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.077898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1546260 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1439342 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3651657500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106918 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 279.697951 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 166500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 46737452 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31992.915413 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29025.659779 # average overall mshr miss latency -system.cpu.dcache.demand_hits 45087250 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 52794773000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.035308 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1650202 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1488860 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4683058000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003452 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 161342 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4074.742226 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994810 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 46737452 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31992.915413 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29025.659779 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 45087250 # number of overall hits -system.cpu.dcache.overall_miss_latency 52794773000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.035308 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1650202 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1488860 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4683058000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003452 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 161342 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 157232 # number of replacements -system.cpu.dcache.sampled_refs 161328 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4074.742226 # Cycle average of tags in use -system.cpu.dcache.total_refs 45123111 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 314584000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 123248 # number of writebacks -system.cpu.decode.BlockedCycles 22792287 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 94517 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 3532335 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 118494504 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 25168271 # Number of cycles decode is idle -system.cpu.decode.RunCycles 21456388 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1835527 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 324840 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 507679 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses +host_inst_rate 54516 # Simulator instruction rate (inst/s) +host_tick_rate 19691005 # Simulator tick rate (ticks/s) +host_mem_usage 264076 # Number of bytes of host memory used +host_seconds 1845.93 # Real time elapsed on the host +sim_insts 100633035 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 17580538 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 11694526 # Number of cache lines fetched -system.cpu.fetch.Cycles 22441550 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 172369 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 87382256 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 923972 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.241798 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 11694526 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 11391827 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.201833 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 71760152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.691303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.918883 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 72696421 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 17573172 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11453458 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 851549 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 14915035 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9554942 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 1842823 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 176515 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 11675232 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87296891 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17573172 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11397765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22503406 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 923751 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 11675232 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 177839 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71670018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.692121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.915842 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 49333953 68.75% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2332887 3.25% 72.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2565274 3.57% 75.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2261875 3.15% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1646575 2.29% 81.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1680171 2.34% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 992700 1.38% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1397961 1.95% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9548756 13.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 49181996 68.62% 68.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2373056 3.31% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2569214 3.58% 75.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2298620 3.21% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1644656 2.29% 81.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1723119 2.40% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 990721 1.38% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1380652 1.93% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9507984 13.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71760152 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 101 # number of floating regfile reads -system.cpu.fp_regfile_writes 77 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 11694526 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12656.148341 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9158.013544 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 11668397 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 330692500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.002234 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 26129 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 231249000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002159 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 25251 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 462.334456 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.fetch.rateDist::total 71670018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.241734 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200842 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 25114154 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 22709447 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21527142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 497633 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1821642 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3527413 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 94287 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118399354 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 324192 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1821642 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26632137 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2439992 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16812666 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20410601 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3552980 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115899857 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 27143 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2453549 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 118034319 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 532748209 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532647632 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 100577 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99142525 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18891789 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 756618 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 756606 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 10359843 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29552116 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22027852 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13146932 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13132796 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 110916590 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 749122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 106735970 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111004 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10702418 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 27336640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 48262 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71670018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.489269 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.647816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26697633 37.25% 37.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17182939 23.98% 61.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10552290 14.72% 75.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7611894 10.62% 86.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5202284 7.26% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2658918 3.71% 97.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1053563 1.47% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 496311 0.69% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 214186 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71670018 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 81861 4.61% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1408075 79.27% 83.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 286311 16.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56941286 53.35% 53.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86568 0.08% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28575402 26.77% 80.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132684 19.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 106735970 # Type of FU issued +system.cpu.iq.rate 1.468242 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1776247 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016642 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 287029038 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122376660 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105058655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 171 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 178 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 108512130 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1096048 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 2243776 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2146 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9239 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1470884 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1821642 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 971169 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 52846 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111742721 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 886869 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29552116 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22027852 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 732058 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3681 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 9239 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 680356 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 238968 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 919324 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 105624762 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28223458 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1111208 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 77009 # number of nop insts executed +system.cpu.iew.exec_refs 49234670 # number of memory reference insts executed +system.cpu.iew.exec_branches 14652571 # Number of branches executed +system.cpu.iew.exec_stores 21011212 # Number of stores executed +system.cpu.iew.exec_rate 1.452957 # Inst execution rate +system.cpu.iew.wb_sent 105223313 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105058729 # cumulative count of insts written-back +system.cpu.iew.wb_producers 51964381 # num instructions producing a value +system.cpu.iew.wb_consumers 99748825 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.445171 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.520952 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 100638587 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11026953 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 700860 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 821298 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 69848377 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.440815 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.128695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31252601 44.74% 44.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 20067748 28.73% 73.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4700774 6.73% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4062261 5.82% 86.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3060219 4.38% 90.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1682719 2.41% 92.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 680213 0.97% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 487977 0.70% 94.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3853865 5.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 69848377 # Number of insts commited each cycle +system.cpu.commit.count 100638587 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 47865307 # Number of memory references committed +system.cpu.commit.loads 27308339 # Number of loads committed +system.cpu.commit.membars 15920 # Number of memory barriers committed +system.cpu.commit.branches 13669858 # Number of branches committed +system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. +system.cpu.commit.int_insts 91477707 # Number of committed integer instructions. +system.cpu.commit.function_calls 1679850 # Number of function calls committed. +system.cpu.commit.bw_lim_events 3853865 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 177634753 # The number of ROB reads +system.cpu.rob.rob_writes 225156428 # The number of ROB writes +system.cpu.timesIdled 61363 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1026403 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633035 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633035 # Number of Instructions Simulated +system.cpu.cpi 0.722391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.722391 # CPI: Total CPI of All Threads +system.cpu.ipc 1.384291 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.384291 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 508078422 # number of integer regfile reads +system.cpu.int_regfile_writes 103555080 # number of integer regfile writes +system.cpu.fp_regfile_reads 153 # number of floating regfile reads +system.cpu.fp_regfile_writes 125 # number of floating regfile writes +system.cpu.misc_regfile_reads 144338885 # number of misc regfile reads +system.cpu.misc_regfile_writes 34300 # number of misc regfile writes +system.cpu.icache.replacements 23105 # number of replacements +system.cpu.icache.tagsinuse 1790.585512 # Cycle average of tags in use +system.cpu.icache.total_refs 11649212 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 25136 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 463.447327 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1790.585512 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.874309 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 11649212 # number of ReadReq hits +system.cpu.icache.demand_hits 11649212 # number of demand (read+write) hits +system.cpu.icache.overall_hits 11649212 # number of overall hits +system.cpu.icache.ReadReq_misses 26020 # number of ReadReq misses +system.cpu.icache.demand_misses 26020 # number of demand (read+write) misses +system.cpu.icache.overall_misses 26020 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 329928500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 329928500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 329928500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 11675232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 11675232 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 11675232 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002229 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002229 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002229 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12679.803997 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12679.803997 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12679.803997 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11694526 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12656.148341 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9158.013544 # average overall mshr miss latency -system.cpu.icache.demand_hits 11668397 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 330692500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.002234 # miss rate for demand accesses -system.cpu.icache.demand_misses 26129 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 231249000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.002159 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 25251 # number of demand (read+write) MSHR misses +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1791.221082 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.874620 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 11694526 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12656.148341 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9158.013544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 11668397 # number of overall hits -system.cpu.icache.overall_miss_latency 330692500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.002234 # miss rate for overall accesses -system.cpu.icache.overall_misses 26129 # number of overall misses -system.cpu.icache.overall_mshr_hits 878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 231249000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.002159 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 25251 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 875 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 875 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 875 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 25145 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 25145 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 25145 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 23207 # number of replacements -system.cpu.icache.sampled_refs 25238 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_mshr_miss_latency 230769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 230769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 230769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.002154 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002154 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002154 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 9177.530324 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1791.221082 # Cycle average of tags in use -system.cpu.icache.total_refs 11668397 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 947358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 921550 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 14656801 # Number of branches executed -system.cpu.iew.exec_nop 77012 # number of nop insts executed -system.cpu.iew.exec_rate 1.452788 # Inst execution rate -system.cpu.iew.exec_refs 49215024 # number of memory reference insts executed -system.cpu.iew.exec_stores 21014437 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 1008310 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29564246 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 729945 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 860230 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 22056705 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 111818970 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28200587 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1136003 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 105628608 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3950 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5079 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1835527 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 47240 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 1083799 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 2228 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 9171 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 2255905 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 1499736 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 9171 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 239261 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 682289 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 99911986 # num instructions consuming a value -system.cpu.iew.wb_count 105081633 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.522057 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 52159787 # num instructions producing a value -system.cpu.iew.wb_rate 1.445265 # insts written-back per cycle -system.cpu.iew.wb_sent 105241173 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 508070420 # number of integer regfile reads -system.cpu.int_regfile_writes 103566970 # number of integer regfile writes -system.cpu.ipc 1.384080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.384080 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56975144 53.37% 53.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86496 0.08% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 3 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28559455 26.75% 80.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21143495 19.80% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106764611 # Type of FU issued -system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 153 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 1795216 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016815 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 87233 4.86% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1425196 79.39% 84.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 282787 15.75% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 108559749 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 287203483 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 105081566 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 122521154 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 110994950 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 106764611 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 747008 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 10770592 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 119046 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 46147 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 27581574 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 71760152 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.487798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.647275 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26733734 37.25% 37.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17263615 24.06% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10576325 14.74% 76.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7516482 10.47% 86.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5241170 7.30% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2631549 3.67% 97.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1101075 1.53% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 499591 0.70% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 196611 0.27% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71760152 # Number of insts issued each cycle -system.cpu.iq.rate 1.468412 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 106906 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.046928 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31243.735685 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 4301 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3529309000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.959768 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205763500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959768 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 79657 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34365.671873 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.753936 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 47389 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1108911500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.405087 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32268 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1001763000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32203 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 157197 # number of replacements +system.cpu.dcache.tagsinuse 4074.737833 # Cycle average of tags in use +system.cpu.dcache.total_refs 45133660 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161293 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 279.824047 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314597000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4074.737833 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994809 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26793039 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18304159 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 19298 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17149 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 45097198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 45097198 # number of overall hits +system.cpu.dcache.ReadReq_misses 104208 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1545742 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1649950 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1649950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2387617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 50445288500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 403500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 52832906000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 52832906000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 26897247 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 19329 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17149 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46747148 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46747148 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.077872 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035295 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035295 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22912.036504 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 32634.998920 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13016.129032 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32020.913361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32020.913361 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 170000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18888.888889 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 123219 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 49816 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1438831 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1488647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1488647 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 54392 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106911 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 161303 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 161303 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1030956000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3651524500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4682480500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4682480500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003451 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003451 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18954.184439 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34154.806334 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 114546 # number of replacements +system.cpu.l2cache.tagsinuse 18280.291791 # Cycle average of tags in use +system.cpu.l2cache.total_refs 68908 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133392 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.516583 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 2302.452210 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15977.839581 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.070265 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487605 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 47261 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123219 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.615385 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 8 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.615385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 123248 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 123248 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.517741 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_hits 4298 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 51559 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 51559 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32262 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 134867 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 134867 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1107753000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3528908000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4636661000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4636661000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 79523 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123219 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 9 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106903 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 186426 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 186426 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.405694 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.444444 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959795 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.723434 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.723434 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34336.153989 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 8500 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34393.138736 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34379.507218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34379.507218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 186563 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34389.540531 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.252300 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 51690 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4638220500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.722935 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 134873 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4207526500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.722587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 134808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2299.680524 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15982.000784 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070181 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487732 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 186563 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34389.540531 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.252300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 51690 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4638220500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.722935 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 134873 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4207526500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.722587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 134808 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 88455 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 63 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32199 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 134804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 134804 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 114549 # number of replacements -system.cpu.l2cache.sampled_refs 133395 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1001736500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205255000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4206991500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4206991500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404902 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.444444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959795 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.723097 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.723097 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31110.795366 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.779787 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18281.681308 # Cycle average of tags in use -system.cpu.l2cache.total_refs 69064 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 88456 # number of writebacks -system.cpu.memDep0.conflictingLoads 13566871 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13247079 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 29564246 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22056705 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 144417750 # number of misc regfile reads -system.cpu.misc_regfile_writes 34302 # number of misc regfile writes -system.cpu.numCycles 72707510 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 2506668 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 99142533 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 23088 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 26680183 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2442887 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 533141286 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 115984519 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 118104117 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 20356223 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1835527 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 3532279 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 18961579 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 100234 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 533041052 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 16849272 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 756028 # count of serializing insts renamed -system.cpu.rename.skidInsts 10368336 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 756038 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 177832725 # The number of ROB reads -system.cpu.rob.rob_writes 225323365 # The number of ROB writes -system.cpu.timesIdled 61505 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |