Regressions: Update regressions for SIMD opclass changes

4 files changed, 192 insertions, 22 deletions

diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index dde0e3f31..a73ef9125 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -136,8 +136,8 @@ size=64
 
 [system.cpu.fuPool]
 type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
@@ -231,41 +231,167 @@ opLat=1
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
 children=opList
 count=0
-opList=system.cpu.fuPool.FUList5.opList
+opList=system.cpu.fuPool.FUList6.opList
 
-[system.cpu.fuPool.FUList5.opList]
+[system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 issueLat=1
 opClass=MemWrite
 opLat=1
 
-[system.cpu.fuPool.FUList6]
+[system.cpu.fuPool.FUList7]
 type=FUDesc
 children=opList0 opList1
 count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
-[system.cpu.fuPool.FUList6.opList0]
+[system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 issueLat=1
 opClass=MemRead
 opLat=1
 
-[system.cpu.fuPool.FUList6.opList1]
+[system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 issueLat=1
 opClass=MemWrite
 opLat=1
 
-[system.cpu.fuPool.FUList7]
+[system.cpu.fuPool.FUList8]
 type=FUDesc
 children=opList
 count=1
-opList=system.cpu.fuPool.FUList7.opList
+opList=system.cpu.fuPool.FUList8.opList
 
-[system.cpu.fuPool.FUList7.opList]
+[system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 issueLat=3
 opClass=IprAccess
@@ -358,7 +484,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
@@ -1,5 +1,11 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 924b5b582..daf9d1530 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov  2 2010 22:35:53
-M5 executing on aus-bc2-b15
+M5 compiled Nov 15 2010 08:52:32
+M5 revision f440cdaf1c2d+ 7743+ default tip
+M5 started Nov 15 2010 13:43:59
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 4056e4f43..71499661d 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 245514                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 249732                       # Number of bytes of host memory used
-host_seconds                                   324.18                       # Real time elapsed on the host
-host_tick_rate                               83167459                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 163173                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215808                       # Number of bytes of host memory used
+host_seconds                                   487.78                       # Real time elapsed on the host
+host_tick_rate                               55274619                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.026962                       # Number of seconds simulated
@@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt        122228      0.14%     56.85% # Ty
 system.cpu.iq.ISSUE:FU_type_0::FloatMult           51      0.00%     56.85% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatDiv         38521      0.05%     56.90% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     56.90% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::MemRead       21679241     25.37%     82.27% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::MemWrite      15152888     17.73%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
@@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     11.00% # at
 system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     11.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     11.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     11.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     11.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::MemRead           404792     44.70%     55.70% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::MemWrite          401115     44.30%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available