diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2011-04-12 16:09:20 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-04-12 16:09:20 -0400 |
commit | d50d0152d0ea40e93c73dec1ffb6f37e79609fdd (patch) | |
tree | c3e2400206e83dd3ca5f36a53ba5e88d31f26ac4 /tests/long/50.vortex | |
parent | 4b61abe8da876ed3e56a1851384ec11ede65bd89 (diff) | |
download | gem5-d50d0152d0ea40e93c73dec1ffb6f37e79609fdd.tar.xz |
ARM: Fix stats for ARM_SE checkpoint restore fix.
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
Diffstat (limited to 'tests/long/50.vortex')
-rw-r--r-- | tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini | 4 | ||||
-rw-r--r-- | tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 14 |
2 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index dfd9d4d58..6767fc19c 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -493,12 +493,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index bb67506e5..2c7e07f74 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 65034 # Simulator instruction rate (inst/s) -host_mem_usage 264616 # Number of bytes of host memory used -host_seconds 1547.38 # Real time elapsed on the host -host_tick_rate 25780112 # Simulator tick rate (ticks/s) +host_inst_rate 216149 # Simulator instruction rate (inst/s) +host_mem_usage 267340 # Number of bytes of host memory used +host_seconds 465.57 # Real time elapsed on the host +host_tick_rate 85683012 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100633305 # Number of instructions simulated sim_seconds 0.039892 # Number of seconds simulated @@ -292,7 +292,7 @@ system.cpu.iew.memOrderViolationEvents 8523 # Nu system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly system.cpu.int_regfile_reads 252839831 # number of integer regfile reads -system.cpu.int_regfile_writes 78127707 # number of integer regfile writes +system.cpu.int_regfile_writes 78127703 # number of integer regfile writes system.cpu.ipc 1.261330 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.261330 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -502,8 +502,8 @@ system.cpu.memDep0.conflictingLoads 15454792 # Nu system.cpu.memDep0.conflictingStores 13946617 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 29744817 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 22207815 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 146355256 # number of misc regfile reads -system.cpu.misc_regfile_writes 34410 # number of misc regfile writes +system.cpu.misc_regfile_reads 146355254 # number of misc regfile reads +system.cpu.misc_regfile_writes 34408 # number of misc regfile writes system.cpu.numCycles 79783473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |