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authorKevin Lim <ktlim@umich.edu>2007-04-27 16:36:19 -0400
committerKevin Lim <ktlim@umich.edu>2007-04-27 16:36:19 -0400
commit71b6499c126632766606fe227a99e06b79ddcc79 (patch)
tree10ef56b74d22307fe49d42f6747615a13197e6c0 /tests/long/50.vortex
parent7f39291c81cb65dc166926136c8f3cab253df160 (diff)
downloadgem5-71b6499c126632766606fe227a99e06b79ddcc79.tar.xz
Updates for clock changes.
--HG-- extra : convert_revision : 88699ba98a738a62204ae4182f7ee5dcab9285eb
Diffstat (limited to 'tests/long/50.vortex')
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini2
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out2
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt12
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr1
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout6
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini2
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out2
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt114
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr1
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout6
10 files changed, 73 insertions, 75 deletions
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 7dbc37b58..7932bf16f 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -12,7 +12,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
-clock=1
+clock=500
cpu_id=0
defer_registration=false
function_trace=false
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
index ee1fc877f..b69343874 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
@@ -47,7 +47,7 @@ progress_interval=0
system=system
cpu_id=0
workload=system.cpu.workload
-clock=1
+clock=500
phase=0
defer_registration=false
width=1
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
index 323b8a93c..37d044e8d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 638506 # Simulator instruction rate (inst/s)
-host_mem_usage 150340 # Number of bytes of host memory used
-host_seconds 213.38 # Real time elapsed on the host
-host_tick_rate 638505 # Simulator tick rate (ticks/s)
+host_inst_rate 644632 # Simulator instruction rate (inst/s)
+host_mem_usage 151548 # Number of bytes of host memory used
+host_seconds 211.36 # Real time elapsed on the host
+host_tick_rate 322315545 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated
-sim_seconds 0.000136 # Number of seconds simulated
-sim_ticks 136246935 # Number of ticks simulated
+sim_seconds 0.068123 # Number of seconds simulated
+sim_ticks 68123467500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 136246936 # number of cpu cycles simulated
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr
index c0f1c1fbb..08cfb2451 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr
@@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x1838c0 length 0x10.
warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x0 length 0x0.
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Ignoring request to flush register windows.
warn: ignoring syscall time(4026527856, 4026528256, ...)
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
index 8e5f7bf90..794510e19 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 21 2007 00:48:18
-M5 started Wed Mar 21 00:48:40 2007
+M5 compiled Apr 27 2007 14:35:32
+M5 started Fri Apr 27 15:55:23 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 136246935 because target called exit()
+Exiting @ tick 68123467500 because target called exit()
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 770dac1b9..1bc14e993 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -12,7 +12,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
cpu_id=0
defer_registration=false
function_trace=false
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
index 30db17922..cb469d872 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
@@ -47,7 +47,7 @@ progress_interval=0
system=system
cpu_id=0
workload=system.cpu.workload
-clock=1
+clock=500
phase=0
defer_registration=false
// width not specified
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
index 78f34213e..4e8db9778 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 473146 # Simulator instruction rate (inst/s)
-host_mem_usage 156372 # Number of bytes of host memory used
-host_seconds 287.96 # Real time elapsed on the host
-host_tick_rate 4801122 # Simulator tick rate (ticks/s)
+host_inst_rate 466766 # Simulator instruction rate (inst/s)
+host_mem_usage 157052 # Number of bytes of host memory used
+host_seconds 291.90 # Real time elapsed on the host
+host_tick_rate 335938336 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated
-sim_seconds 0.001383 # Number of seconds simulated
-sim_ticks 1382530003 # Number of ticks simulated
+sim_seconds 0.098059 # Number of seconds simulated
+sim_ticks 98059078500 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 3241.706786 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2241.706786 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 147462000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 101973000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 3166.666667 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2166.666667 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 47500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 32500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 3588.938331 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2588.938331 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 377463000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 272289000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 3484.100277 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 524925000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 374262000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 3484.100277 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 57944942 # number of overall hits
-system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 524925000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_misses 150663 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 374262000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4090.058697 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 224414000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107279 # number of writebacks
system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 2800.327765 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1800.327765 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 523728500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 336704500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 2800.327765 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency
system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 523728500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 336704500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 2800.327765 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 136059913 # number of overall hits
-system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 523728500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 336704500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 2008.440865 # Cycle average of tags in use
system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.warmup_cycle 69827484000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 2644.770157 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1643.366085 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 356195000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 221326901 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
@@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 2644.770157 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 356195000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 221326901 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 2634.831752 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 309728 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 356195000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 135187 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 221326901 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 101911 # number of replacements
system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 32141.182824 # Cycle average of tags in use
system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle 20627583000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 82918 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1382530003 # number of cpu cycles simulated
+system.cpu.numCycles 98059078500 # number of cpu cycles simulated
system.cpu.num_insts 136246936 # Number of instructions executed
system.cpu.num_refs 58111522 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
index c0f1c1fbb..08cfb2451 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
@@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x1838c0 length 0x10.
warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x0 length 0x0.
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Ignoring request to flush register windows.
warn: ignoring syscall time(4026527856, 4026528256, ...)
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
index dc2b61804..08ec05c3a 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 29 2007 03:55:17
-M5 started Thu Mar 29 03:55:38 2007
+M5 compiled Apr 27 2007 14:35:32
+M5 started Fri Apr 27 15:58:57 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1382530003 because target called exit()
+Exiting @ tick 98059078500 because target called exit()