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authorNathan Binkert <nate@binkert.org>2009-03-07 14:30:55 -0800
committerNathan Binkert <nate@binkert.org>2009-03-07 14:30:55 -0800
commit5cf060576623f3681b497c46934fb4fe6f8853a6 (patch)
treee9b005046f2118e537528178da5f935dc55dc5c1 /tests/long/50.vortex
parentac7bda0212a22d86d9e24665998f294b96869680 (diff)
downloadgem5-5cf060576623f3681b497c46934fb4fe6f8853a6.tar.xz
tests: update tests because of changes in stat names and in the stats package
Diffstat (limited to 'tests/long/50.vortex')
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt64
2 files changed, 38 insertions, 36 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 830b96073..3c4f7e5f4 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:29:46
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
+M5 compiled Mar 6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar 6 2009 18:23:18
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index ea0c05470..c3cb349a5 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,25 +1,21 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 8039250 # Number of BTB hits
-global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
-global.BPredUnit.lookups 16249463 # Number of BP lookups
-global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
-host_inst_rate 207814 # Simulator instruction rate (inst/s)
-host_mem_usage 214944 # Number of bytes of host memory used
-host_seconds 382.99 # Real time elapsed on the host
-host_tick_rate 70849023 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 261905 # Simulator instruction rate (inst/s)
+host_mem_usage 216920 # Number of bytes of host memory used
+host_seconds 303.90 # Real time elapsed on the host
+host_tick_rate 89289765 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027135 # Number of seconds simulated
sim_ticks 27134794500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 8039250 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 16249463 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 17563410 3311.27%
- 1 13937999 2627.76%
- 2 8266125 1558.43%
- 3 4784809 902.09%
- 4 4627568 872.45%
- 5 2066740 389.65%
- 6 1112374 209.72%
- 7 454507 85.69%
- 8 227738 42.94%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11%
+system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28%
+system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58%
+system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02%
+system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72%
+system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90%
+system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10%
+system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86%
+system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43%
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::total 53041270
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333
system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 18483.925058 # Cy
system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120647 # number of writebacks
+system.cpu.memDep0.conflictingLoads 12835812 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11558188 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 54269590 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed