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authorNathan Binkert <nate@binkert.org>2009-04-08 22:21:30 -0700
committerNathan Binkert <nate@binkert.org>2009-04-08 22:21:30 -0700
commit374ba9bae359e68c1496f8db25c38a817af2da19 (patch)
tree48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/long/60.bzip2/ref/alpha/tru64/o3-timing
parente0de2c34433be76eac7798e58e1ae02f5bffb732 (diff)
downloadgem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz
tests: update tests for TLB unification
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/o3-timing')
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini4
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt40
3 files changed, 34 insertions, 18 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 7014f9608..c5cc148d0 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 644c3eb5c..e092c3b04 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:18:05
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:33:27
M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 16f472fdf..3fa048f88 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 226973 # Simulator instruction rate (inst/s)
-host_mem_usage 205820 # Number of bytes of host memory used
-host_seconds 7648.67 # Real time elapsed on the host
-host_tick_rate 97050740 # Simulator tick rate (ticks/s)
+host_inst_rate 226919 # Simulator instruction rate (inst/s)
+host_mem_usage 205788 # Number of bytes of host memory used
+host_seconds 7650.48 # Real time elapsed on the host
+host_tick_rate 97027777 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.742309 # Number of seconds simulated
@@ -131,10 +131,14 @@ system.cpu.decode.DECODE:RunCycles 549143104 # Nu
system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 768331639 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 752318838 # DTB hits
-system.cpu.dtb.misses 16012801 # DTB misses
+system.cpu.dtb.data_accesses 768331639 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 752318838 # DTB hits
+system.cpu.dtb.data_misses 16012801 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 566617551 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 557381525 # DTB read hits
@@ -327,10 +331,22 @@ system.cpu.iq.iqSquashedInstsExamined 739697610 # Nu
system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 355180552 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 355180518 # ITB hits
-system.cpu.itb.misses 34 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 355180552 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 355180518 # ITB hits
+system.cpu.itb.fetch_misses 34 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency