Update Alpha reference stats for clock changes.

tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr:
    Update refs for clock changes.

--HG--
extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42

4 files changed, 68 insertions, 165 deletions

diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 0a123d4a4..2f9e86a73 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -1,48 +1,7 @@
 [root]
 type=Root
 children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
 
 [system]
 type=System
@@ -53,7 +12,7 @@ physmem=system.physmem
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
 cpu_id=0
 defer_registration=false
 function_trace=false
@@ -197,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
 egid=100
 env=
 euid=100
@@ -223,14 +182,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
index 4692c5d40..7cc7b0b90 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
@@ -1,15 +1,13 @@
 [root]
 type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
 
 [system.physmem]
 type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 input=cin
 output=cout
 env=
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
 system=system
 uid=100
 euid=100
@@ -49,7 +47,7 @@ progress_interval=0
 system=system
 cpu_id=0
 workload=system.cpu.workload
-clock=1
+clock=500
 phase=0
 defer_registration=false
 // width not specified
@@ -178,51 +176,3 @@ prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
 hit_latency=1
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
index 45b7beb7c..eb696cc14 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 486900                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1198232                       # Number of bytes of host memory used
-host_seconds                                  3737.50                       # Real time elapsed on the host
-host_tick_rate                                8500130                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 623968                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 154076                       # Number of bytes of host memory used
+host_seconds                                  2916.46                       # Real time elapsed on the host
+host_tick_rate                              423514548                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780129                       # Number of instructions simulated
-sim_seconds                                  0.031769                       # Number of seconds simulated
-sim_ticks                                 31769223012                       # Number of ticks simulated
+sim_seconds                                  1.235165                       # Number of seconds simulated
+sim_ticks                                1235165291000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3121.340330                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2121.340330                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency  2978.629098                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  1978.629098                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    22543612099                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    21512892500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  15321198099                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  14290478500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3602.533807                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2602.533807                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency  2992.340366                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  1992.340366                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    6806339173                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5653488500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   4917019173                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3764168500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3221.115901                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2221.115901                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency  2981.472133                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  1981.472133                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     29349951272                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     27166381000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  20238217272                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  18054647000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3221.115901                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2221.115901                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency  2981.472133                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  1981.472133                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              596212431                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    29349951272                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    27166381000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses              9111734                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  20238217272                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  18054647000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                9107638                       # number of replacements
 system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4091.845274                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4078.615858                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               75264000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle            20287970000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  2244708                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1819780130                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  4089.753117                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  3089.753117                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency  3779.301746                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2779.301746                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             1819779328                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        3279982                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        3031000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  802                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      2477982                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      2229000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             802                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          1819780130                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  4089.753117                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  3089.753117                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency  3779.301746                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2779.301746                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              1819779328                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         3279982                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         3031000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   802                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      2477982                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      2229000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses         1819780130                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  4089.753117                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  3089.753117                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency  3779.301746                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2779.301746                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             1819779328                       # number of overall hits
-system.cpu.icache.overall_miss_latency        3279982                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        3031000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  802                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      2477982                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      2229000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,27 +138,27 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      1                       # number of replacements
 system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                625.996248                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                611.013893                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1819779328                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses           9112536                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  3215.890455                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1919.394872                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency  2722.045846                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1719.036352                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits               6952383                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    6946815413                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency    5880035500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.237053                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses             2160153                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4146186590                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   3713381532                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.237053                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses        2160153                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses      2244708                       # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits      2215611                       # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate     0.012962                       # miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_misses        29097                       # number of WriteReqNoAck|Writeback misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate     0.012962                       # mshr miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses        29097                       # number of WriteReqNoAck|Writeback MSHR misses
+system.cpu.l2cache.Writeback_accesses         2244708                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             2215611                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate       0.012962                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses             29097                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate     0.012962                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses        29097                       # number of Writeback MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_refs                  4.244141                       # Average number of references to valid blocks.
@@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  3215.890455                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1919.394872                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency  2722.045846                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1719.036352                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                6952383                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     6946815413                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     5880035500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.237053                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses              2160153                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   4146186590                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3713381532                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.237053                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses         2160153                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses          11357244                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  3173.148527                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1919.394872                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency  2685.867535                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1719.036352                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits               9167994                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    6946815413                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency    5880035500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.192762                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses             2189250                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   4146186590                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3713381532                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.190200                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses        2160153                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements               2127385                       # number of replacements
 system.cpu.l2cache.sampled_refs               2160153                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32563.117941                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             31158.106837                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 9167994                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle             748591000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle          122436614000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                 1038202                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                      31769223012                       # number of cpu cycles simulated
+system.cpu.numCycles                     1235165291000                       # number of cpu cycles simulated
 system.cpu.num_insts                       1819780129                       # Number of instructions executed
 system.cpu.num_refs                         606571345                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
index 87866a2a5..d0a887867 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
@@ -1 +1,3 @@
 warn: Entering event queue @ 0.  Starting simulation...
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.