diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-15 19:25:35 -0400 |
commit | b85690e239616b703881b7734b0559f61f9eb75e (patch) | |
tree | f144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/long/60.bzip2/ref/alpha/tru64/simple-timing | |
parent | c30e615689148c6e5ecd06e86069cba716dec5e0 (diff) | |
download | gem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz |
update all the regresstion tests for release
--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing')
3 files changed, 62 insertions, 64 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 2f9e86a73..41806d538 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 7cc7b0b90..55a09db2b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index eb696cc14..009ee213d 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 623968 # Simulator instruction rate (inst/s) -host_mem_usage 154076 # Number of bytes of host memory used -host_seconds 2916.46 # Real time elapsed on the host -host_tick_rate 423514548 # Simulator tick rate (ticks/s) +host_inst_rate 637714 # Simulator instruction rate (inst/s) +host_mem_usage 154060 # Number of bytes of host memory used +host_seconds 2853.60 # Real time elapsed on the host +host_tick_rate 886477792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 1.235165 # Number of seconds simulated -sim_ticks 1235165291000 # Number of ticks simulated +sim_seconds 2.529655 # Number of seconds simulated +sim_ticks 2529654621000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2978.629098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1978.629098 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 21512892500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14290478500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2992.340366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1992.340366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5653488500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3764168500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2981.472133 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 27166381000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 18054647000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2981.472133 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.overall_miss_latency 27166381000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_misses 9111734 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 18054647000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.615858 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20287970000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3779.301746 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2779.301746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3031000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2229000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3779.301746 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3031000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2229000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3779.301746 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1819779328 # number of overall hits -system.cpu.icache.overall_miss_latency 3031000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2229000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.013893 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2722.045846 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.036352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5880035500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3713381532 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2722.045846 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5880035500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3713381532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2685.867535 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 9167994 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5880035500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses system.cpu.l2cache.overall_misses 2189250 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3713381532 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2127385 # number of replacements system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31158.106837 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 122436614000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1038202 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1235165291000 # number of cpu cycles simulated +system.cpu.numCycles 2529654621000 # number of cpu cycles simulated system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_refs 606571345 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls |