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authorGabe Black <gblack@eecs.umich.edu>2007-03-11 19:08:38 -0400
committerGabe Black <gblack@eecs.umich.edu>2007-03-11 19:08:38 -0400
commitfd114742c255d626daa86455c360fa695cd2270c (patch)
treed71137d05a83d3d059c99e5f01d98b8ed4f81a0f /tests/long/60.bzip2/ref/alpha/tru64/simple-timing
parentd9c3b636b0f85d5585d7a26ea8d64a2c5b4db024 (diff)
downloadgem5-fd114742c255d626daa86455c360fa695cd2270c.tar.xz
bzip2 is a tru64 regression, not linux
--HG-- rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout extra : convert_revision : c3f5f5b73186cf6e72c1c8418583d3300e04ad8a
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing')
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini236
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out228
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt220
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr1
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout14
5 files changed, 699 insertions, 0 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..0a123d4a4
--- /dev/null
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,236 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
new file mode 100644
index 000000000..4692c5d40
--- /dev/null
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
@@ -0,0 +1,228 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
new file mode 100644
index 000000000..45b7beb7c
--- /dev/null
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -0,0 +1,220 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 486900 # Simulator instruction rate (inst/s)
+host_mem_usage 1198232 # Number of bytes of host memory used
+host_seconds 3737.50 # Real time elapsed on the host
+host_tick_rate 8500130 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.031769 # Number of seconds simulated
+sim_ticks 31769223012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 596212431 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9111734 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244708 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1819779328 # number of overall hits
+system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 802 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use
+system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 9167994 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2189250 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2127385 # number of replacements
+system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1038202 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 31769223012 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
new file mode 100644
index 000000000..87866a2a5
--- /dev/null
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
@@ -0,0 +1 @@
+warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
new file mode 100644
index 000000000..0c5c00118
--- /dev/null
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
@@ -0,0 +1,14 @@
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!