diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/60.bzip2/ref/alpha/tru64 | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64')
8 files changed, 449 insertions, 437 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 8d8bb9386..a93c146ce 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -353,7 +353,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 0be7bd3b3..13489d0ab 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:30:51 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:05:40 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -30,3 +30,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 732922365000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 93a32f882..3840a0336 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 192033 # Simulator instruction rate (inst/s) -host_mem_usage 206980 # Number of bytes of host memory used -host_seconds 9040.35 # Real time elapsed on the host -host_tick_rate 81902195 # Simulator tick rate (ticks/s) +host_inst_rate 115207 # Simulator instruction rate (inst/s) +host_mem_usage 207548 # Number of bytes of host memory used +host_seconds 15068.91 # Real time elapsed on the host +host_tick_rate 48638035 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.740425 # Number of seconds simulated -sim_ticks 740424887500 # Number of ticks simulated +sim_seconds 0.732922 # Number of seconds simulated +sim_ticks 732922365000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 300304269 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 307023866 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 161 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 19915568 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 268271856 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 347819261 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 23893430 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 297651815 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 304473054 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 19905340 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 266187209 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 345286425 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 23890708 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 63188477 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 63402454 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1374695730 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.323769 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.099460 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1362326064 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.335789 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.108307 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 733755921 53.38% 53.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 260590847 18.96% 72.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 127148586 9.25% 81.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 73808717 5.37% 86.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 48837558 3.55% 90.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 32392808 2.36% 92.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 24165844 1.76% 94.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 10806972 0.79% 95.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 63188477 4.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 722221726 53.01% 53.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 260663635 19.13% 72.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 126275090 9.27% 81.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 73614843 5.40% 86.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 49214339 3.61% 90.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 31342415 2.30% 92.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 24208215 1.78% 94.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 11383347 0.84% 95.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 63402454 4.65% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1374695730 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1362326064 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed system.cpu.commit.COM:loads 445666361 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19915049 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19904825 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 631770816 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 616386841 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.853003 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.853003 # CPI: Total CPI of All Threads +system.cpu.cpi 0.844359 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.844359 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency @@ -59,292 +59,292 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 523747084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16905.655994 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11269.981612 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 513424902 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 174503258000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.019708 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 10322182 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 3045892 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 82003654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013893 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7276290 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 521630579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16446.832647 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11014.947389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 511650921 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 164133765000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.019132 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 9979658 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 2703270 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 80149031000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013949 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7276388 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33742.228480 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.275529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 155297365 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 183258665559 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.033791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5431137 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3182597 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 83540626157 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2248540 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6330.872599 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 30366.853399 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 73.096818 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 156412 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65334 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 990224445 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1983988000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 32545.971387 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34322.334946 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155766779 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 161484094789 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.030870 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 4961723 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 2963011 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 68600462724 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.012435 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1998712 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5974.555782 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 30410.724976 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 72.882698 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 121015 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65147 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 723010868 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1981167500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 684475586 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22710.257030 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency -system.cpu.dcache.demand_hits 668722267 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 357761923559 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.023015 # miss rate for demand accesses -system.cpu.dcache.demand_misses 15753319 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6228489 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 165544280657 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.013916 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9524830 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 682359081 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 21793.023000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency +system.cpu.dcache.demand_hits 667417700 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 325617859789 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses +system.cpu.dcache.demand_misses 14941381 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5666281 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 148749493724 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9275100 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997494 # Average percentage of cache occupancy -system.cpu.dcache.occ_%::1 -0.003143 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4085.737319 # Average occupied blocks per context -system.cpu.dcache.occ_blocks::1 -12.874688 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 684475586 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22710.257030 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997469 # Average percentage of cache occupancy +system.cpu.dcache.occ_%::1 -0.002947 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4085.632664 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -12.069593 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 682359081 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 21793.023000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 668722267 # number of overall hits -system.cpu.dcache.overall_miss_latency 357761923559 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.023015 # miss rate for overall accesses -system.cpu.dcache.overall_misses 15753319 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6228489 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 165544280657 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.013916 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9524830 # number of overall MSHR misses +system.cpu.dcache.overall_hits 667417700 # number of overall hits +system.cpu.dcache.overall_miss_latency 325617859789 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses +system.cpu.dcache.overall_misses 14941381 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5666281 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 148749493724 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9275100 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9156903 # number of replacements -system.cpu.dcache.sampled_refs 9160999 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9156983 # number of replacements +system.cpu.dcache.sampled_refs 9161079 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.299976 # Cycle average of tags in use -system.cpu.dcache.total_refs 669639874 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7084220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245460 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 97965081 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 741 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 54990106 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2817972216 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 726420898 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 545630418 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 93906879 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1735 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 4679333 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 771953785 # DTB accesses +system.cpu.dcache.tagsinuse 4079.597867 # Cycle average of tags in use +system.cpu.dcache.total_refs 667684156 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7084801000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2367711 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 93349702 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 598 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 54504022 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2803113220 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 722066213 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 542175542 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 91814713 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1721 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 4734607 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 769403639 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 755880744 # DTB hits -system.cpu.dtb.data_misses 16073041 # DTB misses +system.cpu.dtb.data_hits 753449541 # DTB hits +system.cpu.dtb.data_misses 15954098 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 569575118 # DTB read accesses +system.cpu.dtb.read_accesses 567301584 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 560292416 # DTB read hits -system.cpu.dtb.read_misses 9282702 # DTB read misses -system.cpu.dtb.write_accesses 202378667 # DTB write accesses +system.cpu.dtb.read_hits 558063709 # DTB read hits +system.cpu.dtb.read_misses 9237875 # DTB read misses +system.cpu.dtb.write_accesses 202102055 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 195588328 # DTB write hits -system.cpu.dtb.write_misses 6790339 # DTB write misses -system.cpu.fetch.Branches 347819261 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 356032734 # Number of cache lines fetched -system.cpu.fetch.Cycles 917156426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8668632 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2872343822 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 28362919 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.234878 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 356032734 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 324197699 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.939659 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1468602609 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.955835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.862588 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 195385832 # DTB write hits +system.cpu.dtb.write_misses 6716223 # DTB write misses +system.cpu.fetch.Branches 345286425 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 353801341 # Number of cache lines fetched +system.cpu.fetch.Cycles 911477048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 8513687 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2856997588 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28043242 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.235555 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 353801341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 321542523 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.949045 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1454140777 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.964732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.867668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 907478951 61.79% 61.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48285594 3.29% 65.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31293098 2.13% 67.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 51463172 3.50% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 124103039 8.45% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 68291233 4.65% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 47448055 3.23% 87.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37389871 2.55% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 152849596 10.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 896465106 61.65% 61.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48268270 3.32% 64.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30594278 2.10% 67.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 50900501 3.50% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 123419810 8.49% 79.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 68033881 4.68% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 46960603 3.23% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36759628 2.53% 89.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 152738700 10.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1468602609 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 356032734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35280.127694 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35449.450549 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 356031481 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 44206000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1454140777 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 353801341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35355.537721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35450.495050 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 353800095 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 44053000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1253 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32259000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1246 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32224500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 391243.385714 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 389219.026403 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 356032734 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35280.127694 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency -system.cpu.icache.demand_hits 356031481 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44206000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 353801341 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35355.537721 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency +system.cpu.icache.demand_hits 353800095 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 44053000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1253 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32259000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1246 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32224500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.349473 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 715.720591 # Average occupied blocks per context -system.cpu.icache.overall_accesses 356032734 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35280.127694 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.349132 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 715.022199 # Average occupied blocks per context +system.cpu.icache.overall_accesses 353801341 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35355.537721 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 356031481 # number of overall hits -system.cpu.icache.overall_miss_latency 44206000 # number of overall miss cycles +system.cpu.icache.overall_hits 353800095 # number of overall hits +system.cpu.icache.overall_miss_latency 44053000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1253 # number of overall misses -system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32259000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1246 # number of overall misses +system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32224500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 715.720591 # Cycle average of tags in use -system.cpu.icache.total_refs 356031481 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 715.022199 # Cycle average of tags in use +system.cpu.icache.total_refs 353800095 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12247167 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 283205490 # Number of branches executed -system.cpu.iew.EXEC:nop 130221162 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.544186 # Inst execution rate -system.cpu.iew.EXEC:refs 773252228 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 202589844 # Number of stores executed +system.cpu.idleCycles 11703954 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 281582966 # Number of branches executed +system.cpu.iew.EXEC:nop 129524501 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.553744 # Inst execution rate +system.cpu.iew.EXEC:refs 770699454 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 202312987 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1537746587 # num instructions consuming a value -system.cpu.iew.WB:count 2247853705 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811174 # average fanout of values written-back +system.cpu.iew.WB:consumers 1532271545 # num instructions consuming a value +system.cpu.iew.WB:count 2239351820 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811403 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1247380184 # num instructions producing a value -system.cpu.iew.WB:rate 1.517949 # insts written-back per cycle -system.cpu.iew.WB:sent 2269524166 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21734619 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 17681894 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 621844790 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1243290213 # num instructions producing a value +system.cpu.iew.WB:rate 1.527687 # insts written-back per cycle +system.cpu.iew.WB:sent 2260914368 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21706879 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 16198055 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 619677157 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 21649497 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 234635839 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2626124753 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 570662384 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 37709808 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2286707552 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 438059 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 21613314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 233108974 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2613111960 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 568386467 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 37669869 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2277546807 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 471616 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 36964 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 93906879 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 800629 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 28495 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 91814713 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 777432 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 361620 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 36313428 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 213767 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 285764 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 36261369 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 212351 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 2870017 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 18 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 176178429 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 73730857 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2870017 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3392458 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18342161 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.172329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.172329 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 2343036 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 174010796 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 72203992 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2343036 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3386842 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 18320037 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.184330 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.184330 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1537413633 66.14% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 96 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 239 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 141 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 581325773 25.01% 91.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 205677417 8.85% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1530874605 66.12% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 97 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 138 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 578961528 25.01% 91.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 205380015 8.87% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2324417360 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 13099894 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005636 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2315216676 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 13456867 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005812 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2747666 20.97% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 8624380 65.84% 86.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1727848 13.19% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 2756939 20.49% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 8882759 66.01% 86.50% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1817169 13.50% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1468602609 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.582741 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.758662 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1454140777 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.592154 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.762923 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 577211692 39.30% 39.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 268561729 18.29% 57.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 245516096 16.72% 74.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 137351239 9.35% 83.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 112900190 7.69% 91.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 73000831 4.97% 96.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 43951863 2.99% 99.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 8418123 0.57% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 1690846 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 566783737 38.98% 38.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 267408405 18.39% 57.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 245316156 16.87% 74.24% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 135509048 9.32% 83.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 112013237 7.70% 91.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 72675996 5.00% 96.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 44106984 3.03% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 8043729 0.55% 99.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2283485 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1468602609 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.569651 # Inst issue rate -system.cpu.iq.iqInstsAdded 2495903546 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2324417360 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 1454140777 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.579442 # Inst issue rate +system.cpu.iq.iqInstsAdded 2483587414 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2315216676 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 740504039 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1264443 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 728311196 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1117432 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 323242086 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 316872766 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 356032768 # ITB accesses +system.cpu.itb.fetch_accesses 353801377 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 356032734 # ITB hits -system.cpu.itb.fetch_misses 34 # ITB misses +system.cpu.itb.fetch_hits 353801341 # ITB hits +system.cpu.itb.fetch_misses 36 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -353,106 +353,107 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1884709 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.194422 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.521684 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 65230144918 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1884709 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 59293928362 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1884709 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7277200 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34313.246356 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31139.092194 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5388273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 64815217500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1888927 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 58819472000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259568 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1888927 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363845 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34326.565768 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.856148 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 12489549322 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1884690 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.794335 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31398.574681 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 174907 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 59072651008 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.907196 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1709783 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53684749213 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.907196 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1709783 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7277298 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34312.855500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31137.095153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5437284 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 63136134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.252843 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1840014 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 57292691000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252843 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1840014 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 114023 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34289.699008 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31224.543680 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3909814350 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363845 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11374106205 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 114023 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3560316144 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245460 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2245460 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11887.575431 # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 114023 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2367711 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2367711 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11849.162556 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.418021 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 39831 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.526283 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 27449 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 473494017 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 325247663 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9161909 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34461.554431 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5388273 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 130045362418 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.411883 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3773636 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9161988 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34426.978644 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.038482 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5612191 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 122208785508 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.387448 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3549797 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 118113400362 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.411883 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3773636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 110977440213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.387448 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3549797 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.452605 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.337458 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 14830.970465 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11057.808672 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 9161909 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34461.554431 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.481343 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.322273 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 15772.655639 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10560.226030 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 9161988 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34426.978644 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.038482 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5388273 # number of overall hits -system.cpu.l2cache.overall_miss_latency 130045362418 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411883 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3773636 # number of overall misses +system.cpu.l2cache.overall_hits 5612191 # number of overall hits +system.cpu.l2cache.overall_miss_latency 122208785508 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.387448 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3549797 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 118113400362 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411883 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3773636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 110977440213 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.387448 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3549797 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2759709 # number of replacements -system.cpu.l2cache.sampled_refs 2784305 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2708907 # number of replacements +system.cpu.l2cache.sampled_refs 2733538 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25888.779137 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6732509 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 154525864500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1195751 # number of writebacks -system.cpu.memDep0.conflictingLoads 123998073 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 64478030 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 621844790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 234635839 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1480849776 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 67789415 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 26332.881669 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6905691 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 152081139500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1176798 # number of writebacks +system.cpu.memDep0.conflictingLoads 124506463 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 62743482 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 619677157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 233108974 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1465844731 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 63989148 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 5483545 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 745501679 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 20525033 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1073372 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3564600090 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2755431831 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2063008571 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 531263306 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 93906879 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 30140307 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 686805608 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 1023 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 5522165 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 740664434 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 19930963 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1000685 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3545348406 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2741098331 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2053584906 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 528288951 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 91814713 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 29382701 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 677381943 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 830 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 61497352 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 59537135 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.timesIdled 461191 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 436319 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 731ef059f..28bd594f7 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -152,12 +152,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 34965adea..47358dad4 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:02 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:06:37 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -28,3 +30,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 2705279137000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index a48cc62c7..713e89734 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1190978 # Simulator instruction rate (inst/s) -host_mem_usage 191664 # Number of bytes of host memory used -host_seconds 1527.97 # Real time elapsed on the host -host_tick_rate 1785366772 # Simulator tick rate (ticks/s) +host_inst_rate 1235575 # Simulator instruction rate (inst/s) +host_mem_usage 206704 # Number of bytes of host memory used +host_seconds 1472.82 # Real time elapsed on the host +host_tick_rate 1836801554 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.727991 # Number of seconds simulated -sim_ticks 2727990505000 # Number of ticks simulated +sim_seconds 2.705279 # Number of seconds simulated +sim_ticks 2705279137000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 177812180000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 158727823 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 104943266000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.012448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2000679 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 98941229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.012448 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2000679 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 30657.334367 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency +system.cpu.dcache.demand_hits 596101072 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 282755446000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.015237 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9223093 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 255086167000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.015237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9223093 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.996068 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4079.892573 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.996035 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4079.758997 # Average occupied blocks per context system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 30657.334367 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9470216 # number of overall misses +system.cpu.dcache.overall_hits 596101072 # number of overall hits +system.cpu.dcache.overall_miss_latency 282755446000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.015237 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9223093 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 255086167000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.015237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9223093 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.758997 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244708 # number of writebacks +system.cpu.dcache.warmup_cycle 40990273000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2365949 # number of writebacks system.cpu.dtb.data_accesses 611922547 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 605324165 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.298700 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 611.737435 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.298761 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 611.862910 # Average occupied blocks per context system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.862910 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 168921 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 89460748000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.910592 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1720399 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68815960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1720399 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 5396262 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 95001608000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.252928 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1826954 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 73078160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252928 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1826954 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 111359 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5786716000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 111359 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4454360000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 111359 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2365949 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2365949 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.515193 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5565183 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 184462356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.389283 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3547353 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 141894120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.389283 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3547353 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.438454 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.335641 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 14367.257286 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10998.286802 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.466649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.320836 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 15291.153152 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10513.160578 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5348043 # number of overall hits -system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3764493 # number of overall misses +system.cpu.l2cache.overall_hits 5565183 # number of overall hits +system.cpu.l2cache.overall_miss_latency 184462356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.389283 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3547353 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 141894120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.389283 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3547353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2751986 # number of replacements -system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2701645 # number of replacements +system.cpu.l2cache.sampled_refs 2726277 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1194738 # number of writebacks +system.cpu.l2cache.tagsinuse 25804.313731 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6857112 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 596452524000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1175830 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5455981010 # number of cpu cycles simulated +system.cpu.numCycles 5410558274 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls |