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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:59:35 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:59:35 -0600
commit06c5283930ff1420046cca33bc9b2bbed6e30823 (patch)
treed2263e9127c2fb8a089c254fd7a63d6dc3e056d9 /tests/long/60.bzip2/ref/arm/linux/simple-atomic
parentfe300c6de2bb5c78f34e14787908d0d0640849eb (diff)
downloadgem5-06c5283930ff1420046cca33bc9b2bbed6e30823.tar.xz
ARM: Update SE stats for TLB stats additions
Diffstat (limited to 'tests/long/60.bzip2/ref/arm/linux/simple-atomic')
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/60.bzip2/ref/arm/linux/simple-atomic/simout10
-rw-r--r--tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt32
3 files changed, 35 insertions, 11 deletions
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 94974c5b8..14dc84cb3 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
index 1c7f546c9..9eea795e5 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:40:33
-M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
+M5 compiled Oct 11 2010 18:37:23
+M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
+M5 started Oct 11 2010 18:37:39
+M5 executing on aus-bc3-b4
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 7984cc4d9..11106ff07 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3154654 # Simulator instruction rate (inst/s)
-host_mem_usage 202692 # Number of bytes of host memory used
-host_seconds 541.87 # Real time elapsed on the host
-host_tick_rate 1577328455 # Simulator tick rate (ticks/s)
+host_inst_rate 2718053 # Simulator instruction rate (inst/s)
+host_mem_usage 254288 # Number of bytes of host memory used
+host_seconds 628.91 # Real time elapsed on the host
+host_tick_rate 1359028059 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1709408682 # Number of instructions simulated
sim_seconds 0.854706 # Number of seconds simulated
sim_ticks 854705615000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses